Analysis of DC Self Heating Effect in Stacked Nanosheet Gate-All-Around Transistor

Kang, Min Jae; Myeong, Ilho; Kang, Myounggon; Shin, Hyungcheol

doi:10.1109/edtm.2018.8421495

Cited by 12 publications

(4 citation statements)

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“…Figure 6 displays the measured Rth values of Con-nsFET and JL-nsFET. The default Rth value for a 3-stack nsFET is determined to be approximately 0.43-44 K µW −1 as referenced in [7]. Consequently, the surface resistance of Con-nsFET is adjusted to achieve an Rth of 0.43 K µW −1 , and the same surface resistance condition is applied to measure the Rth of JL-nsFET.…”

Section: With She Analysismentioning

confidence: 99%

“…The heat issue in logic devices arises from the structure of transistors. The transistors in logic devices have been scaling down to increase its density and adopting FinFET and nanosheet (ns) FET structures to improve performance [2][3][4][5][6][7][8][9]. However, in devices with this structure, the entire surface surrounding the channel is basically covered with an insulator, and the insulator has a lower thermal conductivity than silicon.…”

Section: Introductionmentioning

confidence: 99%

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Comparative analysis of junctionless and inversion-mode nanosheet FETs for self-heating effect mitigation

An,

Kim,

Kim

et al. 2023

Semicond. Sci. Technol.

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Artificial intelligence computing requires hardware like central processing units and graphic processing units for data processing. However, excessive heat generated during computations remains a challenge. The paper focuses on the heat issue in logic devices caused by transistor structures. To address the problem, the operational mechanism of the Junctionless Field-Effect Transistor (JLFET) is investigated. JLFET shows potential in mitigating heat-related issues and is compared to other nanosheet (ns) FETs. In the case of JL-nsFET, the change in mobility with increasing temperature is smaller compared to Con-nsFET, resulting in less susceptibility to lattice scattering and thermal resistance (Rth) in self-heating effect situation is 0.43 [K µW−1] for Con-nsFET and 0.414 [K µW−1] for JL-nsFET. The reason why the Rth of JL-nsFET is smaller than that of Con-nsFET is that JL-nsFET uses a source heat injection conduction mechanism and a large heat transfer area by using a bulk channel.

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Section: With She Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Comparative analysis of junctionless and inversion-mode nanosheet FETs for self-heating effect mitigation

An,

Kim,

Kim

et al. 2023

Semicond. Sci. Technol.

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“…The downscaled FETs geometry is continuously evolving from planar MOSFET to nonplanar FinFET [4][5][6], to gate-all-around (GAA) nanowire, and stacked nanosheet FET (NS-FET) [7] for better and improved gate controllability of the structure. The thermal management of the shrinking FETs is an arduous concern due to the self-heating effect (SHE) observed in gate surrounded structures like FinFET, nanowire [8], and NS-FET [9], which will increase device temperature [10]. This will lead toward current degradation and several other thermal reliability problems like hot carrier injection, time-dependent dielectric breakdown, and chip lifetime reduction [11].…”

Section: Introductionmentioning

confidence: 99%

Investigation of ambient temperature and thermal contact resistance induced self-heating effects in nanosheet FET

Rathore¹,

Jaisawal²,

Suryavanshi³

et al. 2022

Semicond. Sci. Technol.

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Self-heating effect (SHE) is a severe issue in advanced nano-scaled devices such as stacked nanosheet field-effect transistors (NS-FET), which raises the device temperature (TD), that ultimately affects the key electrical characteristics, i.e., threshold voltage (VT), DIBL, subthreshold slope (SS), IOFF, ION, etc. SHE puts design constraints in the advanced CMOS logic devices and circuits. In this paper, we thoroughly investigated the impact of ambient temperature and interface thermal contact resistance induced-self heating effect in the NS-FET using extensive numerical simulations. The weak electron-phonon coupling, phonon scattering, and the ambient temperature-induced joule energy directly coupled with thermal contact resistance cause the SHE-induced thermal degradation, which increases the device temperature (TD) and affects the device reliability. The baseline NS-FET is well-calibrated with the experimental data and 3D quantum corrected drift-diffusion coupled hydrodynamic and thermodynamic transport models is used in our TCAD framework to estimate the impact of ambient temperature and interface thermal contact resistance on the device performance. Moreover, we also evaluate the SHE-induced performance comparison of NS-FET with conventional FinFET and found that thermal degradation in NS-FET potentially worsen the electrical characteristics. Thus, a detailed TCAD analysis shows that the ambient temperature and interface thermal contact resistances deteriorate the effective thermal resistance (Reff) and device performance metrics.

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“…22) What's worse, since the channel of the conventional Ge vertically stacked GAA NW pMOSFET is completely wrapped with hafnium oxide (HfO 2 ) that has lower conductivity of 0.35 W (K × m) −1 ] at sub-10 nm thickness, 23) it is hard to dissipate the heat generated by the current. [24][25][26] For these reasons, it is well-known fact that GAA structure is inferior to FinFET structure in terms of heat dissipation, namely SHE. 27,28) Given that the effective hole mobility decreases as the lattice temperature of the channel increases due to SHE, 29) conventional Ge vertically stacked GAA NW pMOSFET is difficult to fully utilize both advantages of the high intrinsic hole mobility from Ge and the high I on from its vertically stacked channel structure.…”

Section: Introductionmentioning

confidence: 99%

Improvement of self-heating effect in Ge vertically stacked GAA nanowire pMOSFET by utilizing Al₂O₃ for high-performance logic device and electrical/thermal co-design

Song

Kim

Kım

et al. 2021

Jpn. J. Appl. Phys.

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For improving self-heating effect (SHE) in Ge vertically stacked gate-all-around (GAA) nanowire (NW) p-type metal-oxide-semiconductor field-effect transistor (pMOSFET), aluminum oxide (Al2O3, alumina) is utilized for gate dielectric layer. From the high thermal conductivity of Al2O3, SHE is significantly improved. In order to validate the proposed device structure, technology computer-aided design simulation is performed through Synopsys Sentaurus three-dimensional tool. As a result, when Al2O3 is incorporated in Ge vertically stacked GAA NW pMOSFET, SHE can be remarkably improved from 534 to 419 K. In addition, the method of simultaneously accomplishing improvement of SHE and low gate leakage current (I gate) have been specifically investigated and proposed with numerous simulation data.

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Analysis of DC Self Heating Effect in Stacked Nanosheet Gate-All-Around Transistor

Cited by 12 publications

References 0 publications

Comparative analysis of junctionless and inversion-mode nanosheet FETs for self-heating effect mitigation

Comparative analysis of junctionless and inversion-mode nanosheet FETs for self-heating effect mitigation

Investigation of ambient temperature and thermal contact resistance induced self-heating effects in nanosheet FET

Improvement of self-heating effect in Ge vertically stacked GAA nanowire pMOSFET by utilizing Al₂O₃ for high-performance logic device and electrical/thermal co-design

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Analysis of DC Self Heating Effect in Stacked Nanosheet Gate-All-Around Transistor

Cited by 12 publications

References 0 publications

Comparative analysis of junctionless and inversion-mode nanosheet FETs for self-heating effect mitigation

Comparative analysis of junctionless and inversion-mode nanosheet FETs for self-heating effect mitigation

Investigation of ambient temperature and thermal contact resistance induced self-heating effects in nanosheet FET

Improvement of self-heating effect in Ge vertically stacked GAA nanowire pMOSFET by utilizing Al2O3 for high-performance logic device and electrical/thermal co-design

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Improvement of self-heating effect in Ge vertically stacked GAA nanowire pMOSFET by utilizing Al₂O₃ for high-performance logic device and electrical/thermal co-design