Analysis of High-<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> Spacer Asymmetric Underlap DG-MOSFET for SOC Application

Abstract

In this paper, asymmetric underlap doublegate (AUDG) MOSFET is studied to analyze the influence of high-k spacer on the intrinsic device parameters. The AUDG-MOSFET architecture offers better device performance, particularly, drain-induced barrier lowering in contrast to the conventional double-gate (DG)-MOSFET. However, the ON current and the distributed resistances for the device increase considerably. The analysis of the device presented here shows that the detrimental effects of the device can be effectively eliminated using high-k spacers. To evaluate the device performance and to study the improvement associated with the use of high-k spacers, different intrinsic parameters are analyzed. These parameters include transconductance (g m ), transconductance generation factor (g m /I d ), intrinsic gain (g m r o ), intrinsic capacitance (C gd , C gs ), resistance (R gd , R gs ), transport delay (τ m ), inductance (L sd ), cutoff frequency ( f T ), and the maximum frequency of oscillation ( f max ), gain bandwidth product, and inverter delay. Index Terms-Asymmetric underlap double-gate (AUDG)FET, high-k, intrinsic parameter spacer.

Physical Insights Into Electric Field Modulation in Dual-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math> </inline-formula> Spacer Asymmetric Underlap FinFET

“…However, the increase in the rise time is almost negligible, as observed in Fig. 16, which is a merit of the DKAU-FinFET over its single high-k spacer counterpart, where the rise time increases significantly [36]. Thus, a suitable alternative is to optimize t sp , as described in the following, based on the type of inner high-k and outer low-k spacer materials used so that the drain current improvement is maximized and the degradation due to parasitic capacitances is minimized.…”

GaN Nanotube FET With Embedded Gate for High Performance, Low Power Applications

“…The inner gate is located at the center of the structure, and surrounded by the inner gate oxide layer. Hf O 2 as the gate oxide layer material provides for high dielectric constant and large band gap width, which can effectively solve the problem of poor reliability caused by the reduction of gate oxide thickness [13], [14]. The source, channel, and drain is formed surrounding the gate oxide layer.…”