18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.
DOI: 10.1109/ipdps.2004.1303135
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Analysis of high-performance floating-point arithmetic on FPGAs

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Cited by 99 publications
(74 citation statements)
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“…Hosting such applications with high precision requirements on FPGAs is an active research area e.g. [15]. Nevertheless, integer based arithmetic requires significantly less area to implement and run significantly faster than IEEE formats [13], and some FPGA-targeting compilers do not support floating point operations.…”
Section: Computational Transformationmentioning
confidence: 99%
“…Hosting such applications with high precision requirements on FPGAs is an active research area e.g. [15]. Nevertheless, integer based arithmetic requires significantly less area to implement and run significantly faster than IEEE formats [13], and some FPGA-targeting compilers do not support floating point operations.…”
Section: Computational Transformationmentioning
confidence: 99%
“…An example of the simplest double-precision FPU from the Tensilica design library requires on the order of 150,000 gates [36]. Even though FPU units support multiplication as well as addition, and therefore would be partially unused in a distributed summation, floating point multiplication is less complicated to implement than addition [37]. Verification is non-trivial for even a circuit of this size and complexity, and this implementation is among the simplest available.…”
Section: B Applicability To Network Operationsmentioning
confidence: 99%
“…Moreover, multiple tradeoffs between latency and area can be exploited which has already been extensively studied for floating point formats [7,17,21]. There exist also parameterized IP cores which offer particularly efficient implementations for a given architecture.…”
Section: Floating Point Numbers On Fpgasmentioning
confidence: 99%