Analysis of instruction-level vulnerability to dynamic voltage and temperature variations

Abstract

Abstract-Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in aggressive CMOS processes. This paper considers challenges and opportunities in identifying this variation and methods to combat it for improved computing systems. We introduce the notion of instruction-level vulnerability (ILV) to expose variation and its effects to the software stack for use in architectural/compiler optimizations. To compute ILV, we quantify the effect of voltage and temperature variations on the performance and power of a 32-bit, RISC, in-order processor in 65nm TSMC technology at the level of individual instructions. Results show 3.4ns (68FO4) delay variation and 26.7x power variation among instructions, and across extreme corners. Our analysis shows that ILV is not uniform across the instruction set. In fact, ILV data partitions instructions into three equivalence classes. Based on this classification, we show how a low-overhead robustness enhancement techniques can be used to enhance performance by a factor of 1.1x−5.5x.

Variation-tolerant OpenMP Tasking on Tightly-coupled Processor Clusters

“…ILV indicates that the classes of instructions have different levels of vulnerability to variations depending on the way they exercise the non-uniform critical paths across the various pipeline stages. For instance, in an in-order RISC core the execution and memory stages are highly vulnerable to dynamic variations, and the memory class has a higher vulnerability in comparison to the logical/arithmetic class [8]. We note that complex high-performance cores such as IBM POWER6 also confirm that vulnerability is not uniform across the instructions set [19].…”

“…As a direct consequence, there are as many types of tasks in a program as there are task directives in its code. In a variability-affected core, ILV [8] is not uniform across the instruction set. In fact, ILV data partitions instructions into three classes: (i) logical/arithmetic class, (ii) memory class, and (iii) multiply/divide class.…”

“…'Higher level' techniques are needed not only to support individual per-core recovery mechanisms, but also to reduce the cost of RCPE across a cluster and thus improve overall IPC. Some higher-level approaches have been proposed to mitigate timing errors on individual instructions [8] as well as sequence of instructions [9]. Such fine granularities are expensive to control due to the need of fast hardware support.…”

“…At higher levels, where instructions come into focus as the most fine-grained abstraction of the processor's functionality, several efforts have tried to characterize and use variability related information. Rahimi et al introduce a notion of Instruction-Level Vulnerability (ILV) [8] to expose dynamic variations and its effects to the software stack. Another technique, operating at the level of sequence, is proposed by Gupta et al [9] to determine sequences of instructions that have a significant impact on timing error rate.…”

“…This method greatly reduces the number of recovery cycles compared to the baseline scheduler of OpenMP [22], consequently instruction per cycle (IPC) of a 16-core processor cluster is increased up to 1.51× (1.17× on average). We evaluate the effectiveness of our approach with various number of cores (4,8,12,16), and across a wide temperature range(∆T=90°C). …”