Analysis of Layout Arrangement for CMOS Oscillators to Reduce Overall Variation on Silicon

Abstract

This investigation demonstrates the analysis of various layout arrangements for oscillator (OSC) realized by CMOS technologies. Moreover, the analysis reveals that the serpentine style of OSC stages attains the minimum output variation on silicon. This investigation is firstly verified by post-layout simulations, comparing the variation with different kinds of layout arrangement for OSC designs, including serpentine layout style, straight layout style, and staggered layout style, etc. The proposed design is then realized using 0.18 µm process to justify the performance, where a straight line layout style and a serpentine layout style of OSC are physically fabricated on the same die. Besides, the on-silicon measurement is conducted to give the comparison for these two different styles of OSC designs. The proposed serpentine layout style attains the lowest layout variation when the variations are not homogeneous in different directions on the same silicon plane.