Analysis of Low Power Low Kickback noise Dynamic Comparators in Pacemakers

Dastagiri, N. Bala; Kishore, K. Hari

doi:10.17485/ijst/2016/v9i44/105324

Cited by 5 publications

(3 citation statements)

References 10 publications

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“…In this paper for multiplication a systematic Vedic multiplier is using Urdhava Tiryagbhyam. this Vedic multiplier occupies less area and performs faster multiplication among the all multipliers [13][14][15][16][17][18][19][20][21]. By using conventional multiplier, it reduces the typical calculation which is difficult to compute the formula Urdhava Tiryagbhyam is applicable for all types of multiplications.…”

Section: Vedic Multipliermentioning

confidence: 99%

Low power and high speed GDI based convolution using Vedic multiplier

Priyanka¹,

Kumar²,

Priya³

et al. 2018

IJET

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Convolution is having extensive area of application in Digital Signal Processing. Convolution supports to evaluate the output of a system with arbitrary input, with information of impulse response of the system. Linear systems features are totally stated by the systems impulse response, as ruled by the mathematics of convolution. Primary necessity of any application to work fast is that rise in the speed of their basic building block. Multiplier, adder is said to be the important building blocks in the process of convolution. As these blocks consumes plentiful time to obtain the response of the system. Several methods are designed to progress the speed of the Multiplier and adder, among all GDI (Gate Diffusion Input) is under emphasis because of faster working and low power consumption. In this paper GDI based convolution is implemented using Vedic multiplier and adder in T-SPICE Software which increases the speed and consumes less power compared to CMOS technology.

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Section: Vedic Multipliermentioning

confidence: 99%

Low power and high speed GDI based convolution using Vedic multiplier

Priyanka¹,

Kumar²,

Priya³

et al. 2018

IJET

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“…In this way, we get a total of 128 outputs from the comparison module each single output for 128 inputs. The distinct four inputs are combined to get a single output [14][15][16][17][18][19][20][21][22]. This procedure is tracked until we get our last 3 outputs.…”

Section: Architecturementioning

confidence: 99%

CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

Prasanna¹,

Sahiti²,

Raghuveera³

et al. 2018

IJET

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A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs.

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“…So, these became the building blocks of any ADCs. The comparators small voltage variations in ADC's inputs, breakdown the performance and also the preciseness of any ADCs that are mainly found in peak detectors [2][5]. To speed up these dynamic comparators are operated on the feedback.…”

Section: Introductionmentioning

confidence: 99%

Low Voltage High Performance Comparator

Kumar*,

Prabhakar,

Vardhan

et al. 2019

IJITEE

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A comparator has been proposed using the dynamic bias concept. The proposed comparator operates on low power with minimum delay. It describes the comparison of power and delay characteristics between the dynamic bias model, elzakker circuit and two stage dynamic comparator circuits. This is achieved by enhancing the total effective transconductance with in the circuit. All these circuits were simulated at 130nm technology with a supply voltage of 1.2V

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Analysis of Low Power Low Kickback noise Dynamic Comparators in Pacemakers

Cited by 5 publications

References 10 publications

Low power and high speed GDI based convolution using Vedic multiplier

Low power and high speed GDI based convolution using Vedic multiplier

CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

Low Voltage High Performance Comparator

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