Analysis of Magnetically Coupled All-Pass Network for Phase-Shifter Design

Li, Hsiao Yun; Fu, Jia

doi:10.1109/tmtt.2014.2334065

Cited by 26 publications

(17 citation statements)

References 24 publications

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“…As indicated in Section 1, APNs have been used for realising phase shifters [14,[20][21][22][23][24]. The theoretical basis of using APNs for a phase shifter design can be found in [14] and is revisited in Section 2 of [21]. The key result of the analysis is that, if the inductance L and capacitance C in the APN are chosen so that the condition…”

Section: Discussionmentioning

confidence: 99%

“…[18,20]. Comparing these two topologies, the former has the advantages of providing a larger amount of phase shift and exhibits better return loss, whereas the latter occupies less circuit area and often causes lower insertion loss [21]. In this work, we focus ourselves on the second topology, that is, the one with internal switched capacitors.…”

Section: Discussionmentioning

confidence: 99%

“…The schematic is the same as Fig. 16 in [21]. Implementing the 180°bit using SPDT switches is advantageous because it requires little chip area and, more importantly, provides a nearly ideal phase shift response.…”

Section: °Phase-shifting Bitmentioning

confidence: 99%

“…Phase shifters are essential building blocks of phased arrays, which are widely used in applications where beam steering is desired, for example, radars. Common circuit topologies used for phase shifter design include loaded line [1][2][3][4][5], reflection type [6][7][8], vector summing [9][10][11][12][13] and switched network [14][15][16][17][18][19][20][21]. Loaded-line and reflection-type phase shifters are based on transmission lines and therefore the circuit size is usually large for radar bands that are below 10 GHz, for example, L-, S-and C-bands.…”

Section: Introductionmentioning

confidence: 99%

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Broadband complementary metal‐oxide semiconductor phase shifter with 6‐bit resolution based on all‐pass networks

2015

IET Microwaves, Antennas & Propagation

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Multi‐stage all‐pass networks can be used to realise broadband phase shifters with low phase error. In this study, single‐stage and two‐stage all‐pass networks with internal switched capacitors are investigated. Potentials and limitations of using the all‐pass networks with internal switched capacitors for phase shifter design are examined. On the basis of the single‐stage and two‐stage all‐pass networks, a fully‐differential digital phase shifter with 6‐bit resolution is designed. The digital phase shifter is implemented using a 0.18‐μm complementary metal‐oxide semiconductor process. The chip area is 2.80 × 1.75 mm2. Measurement results show that minimum root‐mean‐square phase error of 2° is achieved from 2.19 to 2.82 GHz, which translates into a bandwidth (BW) of 25%. The average insertion loss is 14.6 dB at the design frequency of 2.4 GHz. Over the entire BW, the return loss is greater than 9.2 dB and the amplitude error is within ±1 dB.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Section: °Phase-shifting Bitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Broadband complementary metal‐oxide semiconductor phase shifter with 6‐bit resolution based on all‐pass networks

2015

IET Microwaves, Antennas & Propagation

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“…The digital phase shifter offers comparatively wide‐band phase shift accuracy, ease of implementation, and hence is a widely used phase shifter topology. A 4‐bit, broadband, digital passive phase shifter using magnetically coupled all‐pass network has been experimentally demonstrated, but only with the 4‐bit resolution it occupies a large area, introduces large insertion loss, and has large root mean square (RMS) phase error, as shown in Table .…”

Section: Introductionmentioning

confidence: 99%

Low‐loss 7‐bit S‐band CMOS passive phase shifter with digital control

Kumar

Garg

Selvaraja

et al. 2019

Circuit Theory & Apps

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Summary This paper presents the design and implementation of a 7‐bit S‐band digital passive phase shifter using Complementary Metal‐Oxide‐Semiconductor (CMOS) 65‐nm technology in 2.6‐ to 3.2‐GHz frequency band. New switched delay network topology has been used for 5.625° and 2.8°, and modified switched filter topology has been used for implementation of other phase bits to achieve 7‐bit performance with low insertion loss and better isolation. The measured results of the fabricated chip show 7‐bit performance with an average insertion loss of 11 dB, average root mean square (RMS) phase error of less than 2.0°, average RMS amplitude error of less than 0.6 dB, input matching (S11) better than −7.5 dB, and output matching (S22) better than −14.5 dB across the target frequency band at 50Ω input/output impedance.

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