Analysis of microbump induced stress effects in 3D stacked IC technologies

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps

“…The figure 6 (b) shows the FEM simulation result 978-1-4673-0145-9/12/$31.00 ©2012 IEEE depicting the behavior of the die to die stack in the µbump region after structures cooling from bonding temperature (250ºC) to room temperature [5]. In case of several µbump arrays a wavelike pattern can be expected on the top thin Si die as showed in figure 6 (c) [6]. Figure 6.…”

“…[4][5][6][7][8] Figure 7 (a) illustrates the Fammos simulation results of TSV induced stress components projected on orthogonal axes versus distance from device center to TSV center [8]. For a device with current flowing at horizontal direction as shown on figure 5, the stress component at x direction σ XX is a positive tensile stress and σ YY at y direction is a negative compressive stress.…”

“…Figure 6. Simulated bending of the top thin Si die after stack cooling from bonding temperature [5,6].…”

“…A W/L= 800/600nm transistors array is placed on top of µbump. The Ion current variation is clearly shown on the FET array with µbump compare to the REF reference array without µbump (Figure 10) [6]. In this particular case for the µbump, an increase of 40% of the drain current was measured for a 3D stack using an unfilled polymer underfill material and a 25µm thick TSV die [5, 6 and 9].…”

“…By using a combined experimental and theoretical approach, we provided a framework that will enable stress-aware design and the right definition of keep-out-zone which ultimately saves valuable silicon area [4]. The stress induced by µ-bumps technology also greatly influence the performance of FEOL devices [5,6] and this significant contribution is analyzed in section IV. The via-middle Cu TSVs approach and die to die stacking options are described in Figure 2.…”