Analysis of neutron sensitivity and data-flow error detection in ARM microprocessors using NEON SIMD extensions

Lindoso, Almudena; García-Valderas, M.; Entrena, Luis

doi:10.1016/j.microrel.2019.06.038

Cited by 5 publications

(3 citation statements)

References 15 publications

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“…Exception's handling is also studied in [6] where Pthreads and Openmp parallel frameworks are evaluated for the dual core cortex A9. We can also find other works that present hardening techniques [7], evaluate operating systems behaviour [8] or explore specific parts of the microprocessors [9][10] but to the best of our knowledge no detailed exception behaviour analysis has been presented before.…”

Section: Cots (Components Offmentioning

confidence: 99%

Evaluating reliability through soft error triggered exceptions at ARM Cortex-A9 microprocessor

Avilés

Lindoso

Belloch

et al. 2021

Microelectronics Reliability

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Section: Cots (Components Offmentioning

confidence: 99%

Evaluating reliability through soft error triggered exceptions at ARM Cortex-A9 microprocessor

Avilés

Lindoso

Belloch

et al. 2021

Microelectronics Reliability

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“…The performance overhead produced by data replication techniques can be reduced by exploiting the parallel processing capabilities of SIMD co-processors, which are commonly found in modern microprocessors. SIMD acceleration for replicated data computation has been proposed previously in [16]. An SIMD co-processor has its own register file made of wide registers that can store multiple data to be processed in parallel.…”

Section: A Data Hardening With Neon Simd Co-processormentioning

confidence: 99%

Error Detection and Mitigation of Data-Intensive Microprocessor Applications Using SIMD and Trace Monitoring

Pena-Fernandez

Lindoso

Entrena

et al. 2020

IEEE Trans. Nucl. Sci.

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This work proposes a software error mitigation approach that uses the SIMD coprocessor to accelerate computation over redundant data. In addition, an external IP connected to the microprocessor's trace interface is used to detect errors that are difficult to cover with software-implemented techniques. The proposed approach has been implemented in an ARM microprocessor and an irradiation campaign with neutrons has been carried out at Los Alamos National Laboratory. Experimental results demonstrate the high error coverage (more than 99.9%) of the proposed approach. The neutron cross section of errors that were not corrected nor detected was reduced by more than three orders of magnitude.

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“…Subsequently, several chip vendors have also integrated SIMD vector units on their processors, such as AMD's 3dNow! [4]; Alpha's MVI extension [5]; PowerPC's AltiVec extension [6]; ARM's NEON [7]; MIPS's ASE extension [8]; and Intel's subsequent development of 128-bit wide SIMD extensions (SSE, SSE2, SSE3, SSSE3, SSE4.1, and SSE4.2) [9], 256-bit wide advanced vector extensions (AVX, AVX2) [10], and 512-bit wide advanced vector extensions (AVX3) [1].…”

Section: Introductionmentioning

confidence: 99%

Vectorization Programming Based on HR DSP Using SIMD

Xie

Zhou

2023

Electronics

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Single instruction multiple data (SIMD) vector extension has become an essential feature of high-performance processors. Architectures such as x86, ARM, MIPS, and PowerPC have specific vector extension instruction sets and SIMD micro-architectures. Using SIMD vectorization programming can significantly improve the performance of application algorithms while keeping the hardware overhead low. In addition, other methods can enhance algorithm performance, such as selecting the best SIMD vectorization model for algorithms, ensuring sufficient instruction streams, implementing reasonable and effective cache data prefetching, and aligning data access and storage addresses according to instruction characteristics. The goal of this paper is three-fold. First, we introduce the basic structural characteristics of a general RISC processor, Hua Rui (HR) DSP, with a custom vector instruction set based on compatibility with an MIPS64 fixed-point and floating-point instruction set, as well as a Fei Teng (FT) processor compatible with an ARMv8 instruction set. Second, we summarize the fundamental principles of SIMD vectorization programming design for the HR DSP, which provides ideas for other scholars or engineering and technical personnel to study the algorithm performance using SIMD vectorization optimization. Third, we implement representative typical algorithms based on the HR and FT platforms and obtain experimental results that show improvement in algorithm SIMD vectorization optimization according to the vector programming design principles summarized in this article can improve the single-core performance of scalar implementation without vectorization, instruction streams, and cache data prefetching by 4–22 times for mean filter, accumulation, and matrix–matrix multiplication, which is significantly better than the performance improvement of 3–13 times for the FT platform. Moreover, the performance of matrix–matrix multiplication using the best vectorization model on the HR platform is about 84% higher than that of the common SIMD vectorization model.

show abstract

Analysis of neutron sensitivity and data-flow error detection in ARM microprocessors using NEON SIMD extensions

Cited by 5 publications

References 15 publications

Evaluating reliability through soft error triggered exceptions at ARM Cortex-A9 microprocessor

Evaluating reliability through soft error triggered exceptions at ARM Cortex-A9 microprocessor

Error Detection and Mitigation of Data-Intensive Microprocessor Applications Using SIMD and Trace Monitoring

Vectorization Programming Based on HR DSP Using SIMD

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