Analysis of parameter-independent PLLs with bang-bang phase-detectors

Abstract

The parameter-independent design of Phase-Locked Loops (PLLs) is investigated for the case that a bang-bang phase-detector is used. Two self-biased CMOS PLL structures are proposed and compared, one leading to a completely parameter-and frequency independent behavior. If the PLL frequency operation is constant and known in advance, however, both structures can be made independent of the transistor Vt and b parameters. AbstractThe parameter-independent design of Phase-Locked Loops (PLLs) is investigated for the case that a bangbang phase-detector is used. Two self-biased CMOS PLL structures are proposed and compared, one leading to a completely parameter-and frequency independent behavior. If the PLL frequency operation is constant and known in advance, however, both structures can be made independent of the transistor V t and b parameters.

Analysis of bang-bang clock and data recovery

“…An exception is the work by Walker [1], which illustrates the influ ence o f non-linear phenomena on loop behavior for the first and second order loops.Another work by Jri Lee[29][30] discusses an approximated formula for jitter perfor mance for the non-linear CDR and M. Ramezani[31]-[33] discusses the lock-in-frequency range, lock-in phase and jitter performance o f the second order loop. Thus, very few ana lytical design aids that predict nonlinear behavior can be found for nonlinear CDR[32]-[37]. Many researchers have observed experimental phenomena for which, to date, no analytical explanations exit.…”