Analysis of Parasitics on CMOS based Memristor Crossbar Array for Neuromorphic Systems

Thomas, Sherin Ann; Vohra, Sahibia Kaur; Kumar, Rahul; Sharma, Rohit; Das, Devarshi Mrinal

doi:10.1109/mwscas47672.2021.9531867

Cited by 9 publications

(1 citation statement)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Higher the number of parasitic components on a current path, larger is its propagation delay [70,86,88,89,91]. Parasitic components on bitlines and wordlines are a major source of latency at scaled process technology nodes and they create significant latency variation in a crossbar [33,34,49,53,56,67,79,83,87]. Such variation can introduce ISI distortion (Section B), which may impact the quality of an inference task [9,27].…”

Section: Introductionmentioning

confidence: 99%

Design-Technology Co-Optimization for NVM-based Neuromorphic Processing Elements

Song¹,

Balaji²,

Das³

et al. 2022

Preprint

View full text Add to dashboard Cite

An emerging use-case of machine learning (ML) is to train a model on a high-performance system and deploy the trained model on energy-constrained embedded systems. Neuromorphic hardware platforms, which operate on principles of the biological brain, can significantly lower the energy overhead of a machine learning inference task, making these platforms an attractive solution for embedded ML systems. We present a designtechnology tradeoff analysis to implement such inference tasks on the processing elements (PEs) of a Non-Volatile Memory (NVM)-based neuromorphic hardware. Through detailed circuit-level simulations at scaled process technology nodes, we show the negative impact of technology scaling on the information-processing latency, which impacts the quality-of-service (QoS) of an embedded ML system. At a finer granularity, the latency inside a PE depends on 1) the delay introduced by parasitic components on its current paths, and 2) the varying delay to sense different resistance states of its NVM cells. Based on these two observations, we make the following three contributions. First, on the technology front, we propose an optimization scheme where the NVM resistance state that takes the longest time to sense is set on current paths having the least delay, and vice versa, reducing the average PE latency, which improves the QoS. Second, on the architecture front, we introduce isolation transistors within each PE to partition it into regions that can be individually power-gated, reducing both latency and energy. Finally, on the system-software front, we propose a mechanism to leverage the proposed technological and architectural enhancements when implementing a machine-learning inference task on neuromorphic PEs of the hardware. Evaluations with a recent neuromorphic hardware architecture show that our proposed design-technology co-optimization approach improves both performance and energy efficiency of machine-learning inference tasks without incurring high cost-per-bit. CCS Concepts: • Hardware → Neural systems; Emerging languages and compilers; Emerging tools and methodologies; • Computer systems organization → Data flow architectures; Neural networks.

show abstract