Analysis of Performance Dependencies in NUCA-Based CMP Systems

Abstract

Improvements in semiconductor nanotechnology have continuously provided a crescent number of faster and smaller per-chip transistors. Consequent classical techniques for boosting performance, such as the increase of clock frequency and the amount of work performed at each clock cycle, can no longer deliver to significant improvement due to energy constrains and wire delay effects. As a consequence, designers interests have shifted toward the implementation of systems with multiple cores per chip (Chip Multiprocessors, CMP). CMP systems typically adopt a large last-level-cache (LLC) shared among all cores, and private L1 caches. As the miss resolution time for private caches depends on the response time of the LLC, which is wire-delay dominated, performance are affected by wire delay. NUCA caches have been proposed for single and multi core systems as a mechanism for such tolerating wire-delay effects on the overall performance. In this paper, we introduce our design for S-NUCA and D-NUCA cache memory systems, and we present an analysis of an 8-cpu CMP system with two levels of cache, in which the L1s are private, while the L2 is a NUCA shared among all cores. We considered two different system topologies (the first with the eight cpus connected to the NUCA at the same side -8p-, the second with half of the cpus on one side and the others at the opposite side -4+4p), and for all the configurations we evaluate the effectiveness of both the static and dynamic policies that have been proposed. Our results show that adopting a D-NUCA scheme with the 8p configuration is the best performing solution among all the considered configurations, and that for the 4+4p configuration the D-NUCA outperforms the S-NUCA in most of the cases. We highlight that performance are tied to both mapping strategy variations (Static and Dynamic) and topology changes. We also observe that bandwidth occupancy depends on both the NUCA policy and topology

Memory organizations for 3D-DRAMs and PCMs in processor memory hierarchy

“…Again, we use the name in the first column of the table to refer to the corresponding mix of 4 benchmarks. 3 Chart 5. Average latencies for DRAMs.…”

“…This configuration can be further improved with more intelligent placement of pages in 3D-DRAM and PCM, or migrate pages between these devices. It should be noted that such migrations have some similarities with NUCA caches such as [3,4]. However, unlike NUCAs, pages cannot be replicated in 3D DRAM and PCM.…”

Re-NUCA: Boosting CMP Performance Through Block Replication

“…Instead, in this paper we propose a solution that makes block migration effective in boosting performance while maintaining scalability, since the limited replication mechanism of Re-NUCA allows at most two L2 copies of a shared block without taking care of how many processors are sharing it. As the replication mechanism we introduce extends the behaviors of a classical D-NUCA, we considered the migration scheme with the FMA and Collector optimizations proposed in [29]. The architecture adopts a directory version of MESI as the baseline coherence protocol, in which the directory is non-blocking [19,20,21] and distributed.…”

“…During the time interval in which a block is moving from the source to the destination bank, it is important to manage subsequent requests that could be issued by other L1 caches. A false miss [7,29] is a race condition that can arise when a subsequent request for a migrating block is received from the sender after the block has been issued (and the corresponding cache line has been deallocated), and by the receiver before the block has arrived. Such condition results in an extra off-chip access even if the referred block is actually cached.…”

Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors

“…This policy, called Dynamic NUCA or D-NUCA, achieves lower access latencies than S-NUCA but complicates the process of requesting a block to the LLC, leading to a tradeoff between access time and NoC traffic since all the banks of a bank set must be accessed, leading to either high latency (sequential search) or more traffic (parallel search). Furthermore, it was proposed for a single-core system, and its extension to CMPs does not show the expected performance improvements due to various issues that have to be managed when multiple cores are sharing the same D-NUCA, such as the ping-pong behavior and the race conditions which lead to false and multiple misses [11], [26].…”