Analysis of Power Consumption and BER of Flip-flop Based Interconnect Pipelining

Abstract

Abstract

Improved ber performance in intra-chip rf/wireless interconnect systems

“…3. This system consists of a binary phase-shift keying (BPSK) modulator, a power amplifier (PA), a low noise amplifier (LNA), a BPSK demodulator, a transmit antenna and a receive antenna [9]. Signals in this system go though the dielectric waveguide which is imperfect in nature.…”

“…Besides, the time delay spread of the intra-chip wireless channel is found to be very low compared to the data rate at 15 GHz. So, the channel becomes a non-dispersive Ricean fading in characteristics and in this channel, system performance depends on the signal-to-noise ratio of the received signal at the receiver [9].…”

“…So, increasing the signal power is a possible way to take advantage of channel coding in an intra-chip interconnect. But, this approach results in extra heat generation which eventually affects the realization of the wireless interconnect system [9]. So, it is very important to construct a channel coding scheme which will be easier to implement and will provide better BER performance in intra-chip channel.…”

“…Another alternative is to adopt multi-cycle signal communication, where the delay of a wire exceeds a single clock period. The idea is to divide a wire, whose delay is longer than one clock cycle, into several segments by inserting sequential elements to store signal values that require multiple clock cycles to travel through a particular global wire -a concept that has become known as interconnect pipelining [8] [9]. Some of these hardwired based approaches will find their way into design practice once the implementation challenges are resolved.…”