Analysis of Power Consumption and Linearity in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs

Saberi, Mehdi; Lotfi, Reza; Mafinezhad, Khalil; Serdijn, Wouter A.

doi:10.1109/tcsi.2011.2107214

Cited by 202 publications

(122 citation statements)

References 28 publications

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“…The parasitic capacitances between the top plates and a reference voltage contribute to C par;top (see Fig. 2), which attenuates the DAC output independently of the code, then causing a gain error without degrading the converter linearity [15]. Also the stray capacitances between the bottom-plates and a reference voltage do not contribute to conversion errors since they are directly driven by the SAR logic drivers.…”

Section: Converter Topologiesmentioning

confidence: 99%

“…On the contrary, the capacitor mismatch causes a statistical error. Indeed, analytic expressions are available to estimate the maximum standard deviation of DNL and INL [15,6]. In fact, the capacitive mismatch can be modeled assuming a Gaussian probability distribution of the unit capacitor value with a mean equal to the nominal capacitance, C u , and a standard deviation of…”

Section: Converter Topologiesmentioning

confidence: 99%

“…Under this assumption and considering a single-ended CBW array, the maximum DNL standard deviation occurs at the mid-code and is given by [15] σ DNL;CBW ¼ 2…”

Section: Classic Binary Weighted Array (Cbw)mentioning

confidence: 99%

“…m ¼ l ¼ N=2) and C att ¼C u . In fact, this topology leads to the most energy efficient solution [15]. It has been shown that the BWA topology is more sensitive than CBW topology to capacitor mismatch when the same unit capacitance is employed.…”

Section: Binary Weighted With Attenuation Capacitor (Bwa)mentioning

confidence: 99%

“…1). Impact of mismatch on Differential-Non-Linearity (DNL) and Integral-Non-Linearity (INL) of the most generally adopted array topologies have been studied and formulae are available in the literature [15]. However, no quantitative guideline is available to address nonlinearities arising from parasitic capacitances.…”

Section: Introductionmentioning

confidence: 99%

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An efficient tool for the assisted design of SAR ADCs capacitive DACs

et al. 2016

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a b s t r a c tThe optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic capacitance effects in the feedback charge redistribution DAC. Since both contributions depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a MATLAB-based numerical environment to assist the design of the charge redistribution DACs adopted in SAR ADCs. The tool performs both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances computing both differential and integral nonlinearity (DNL, INL). An excellent agreement is obtained with the results of circuit simulators (e.g. Cadence Spectre) featuring up to 10 4 shorter simulation time, allowing statistical simulations that would be otherwise impracticable. The switching energy and SNDR degradation due to static nonlinear effects are also estimated. Simulations and measurements on three designed and two fabricated prototypes confirm that the proposed tool can be used as a valid instrument to assist the design of a charge redistribution SAR ADC and to predict its static and dynamic metrics.

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Section: Converter Topologiesmentioning

confidence: 99%

Section: Converter Topologiesmentioning

confidence: 99%

“…Under this assumption and considering a single-ended CBW array, the maximum DNL standard deviation occurs at the mid-code and is given by [15] σ DNL;CBW ¼ 2…”

Section: Classic Binary Weighted Array (Cbw)mentioning

confidence: 99%

Section: Binary Weighted With Attenuation Capacitor (Bwa)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An efficient tool for the assisted design of SAR ADCs capacitive DACs

et al. 2016

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Optimal Weight‐Splitting in Resistive Random Access Memory‐Based Computing‐in‐Memory Macros

Song

Kim

Jeong

2022

Advanced Intelligent Systems

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Deep learning (DL) prevalently applies to many tasks that are used to be done using a set of instructions. The improvement of DL capability is desired, which requires the deep neural network (DNN) to be deeper and larger. The wide use of DL with deep and large DNNs causes an immense workload for hardware, which is expected to continue onward. To support this trend, new hardware that accelerates major DL operations with reduced power consumption is strongly demanded. The current mainstream hardware for DL is general-purpose graphics processing units (GPGPUs), which enable parallel multiply-accumulate (MAC) operations-a major operational workload-but consume enormous power. DL accelerators aim to achieve high performance and power efficiency beyond GPGPUs.Several DL accelerators (popularly, referred to as neural processing units) have already been commercialized. [1,2] A nextgeneration (but not far) DL acceleration is considered to be based on the memory-centric architecture that minimizes data movement by computing data near or in memory domains, which is known to consume an immense amount of power. [3] Near-data processing (NDP) realizes parallel floating-point MAC operations in the vicinity of the memory domain, minimizing data movement. [4,5] However, this architecture also suffers from the notorious memory wall issue [6] due to large latency in access to random access memory (RAM). Additionally, NDP leverages its advantages only for memory-bound models, e.g., fully connected networks and recurrent neural networks, where one weight is used for one operation, unlike convolutional neural networks in which one weight is used for many operations.A workaround solution is to merge processing and memory domains into a single domain in which parallel MAC operations are executed in an analog manner. [7][8][9][10][11][12][13][14][15][16][17][18] This strategy realizes inplace MAC operations that allow memory access and operations to occur simultaneously in the same domain. We refer to this strategy as analog computing-in-memory (aCIM). Its feasibility has been demonstrated with various types of memory such as volatile memory, e.g., dynamic RAM, [7] static RAM, [8][9][10] and nonvolatile memory, e.g., magnetic RAM, [11] resistive RAM (RRAM). [12,13,[15][16][17] Among various embedded memories for aCIM, resistance-based nonvolatile RAMs have been attracting large attention because of their feasible analog MAC operations in parallel based on Kirchhoff 's current law (KCL). Particularly, RRAM offers multilevel data representations, so that a single RRAM cell can represent a multi-bit weight, which allows parallel fixed-point MAC operations at reduced space and computational complexities. However, the larger the parallelism and the number of levels of a single cell, the more likely a higher bit-resolution is required for the analog-to-digital converters (ADCs) to avoid data loss, which causes prohibitive power consumption and area overhead.In this regard, it may be necessary to limit the number of levels of a single cell and ...

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PowerGAN: A Machine Learning Approach for Power Side‐Channel Attack on Compute‐in‐Memory Accelerators

Wang,

Wu,

Park

et al. 2023

Advanced Intelligent Systems

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Analog compute‐in‐memory (CIM) systems are promising candidates for deep neural network (DNN) inference acceleration. However, as the use of DNNs expands, protecting user input privacy has become increasingly important. Herein, a potential security vulnerability is identified wherein an adversary can reconstruct the user's private input data from a power side‐channel attack even without knowledge of the stored DNN model. An attack approach using a generative adversarial network is developed to achieve high‐quality data reconstruction from power leakage measurements. The analyses show that the attack methodology is effective in reconstructing user input data from power leakage of the analog CIM accelerator, even at large noise levels and after countermeasures. To demonstrate the efficacy of the proposed approach, an example of CIM inference of U‐Net for brain tumor detection is attacked, and the original magnetic resonance imaging medical images can be successfully reconstructed even at a noise level of 20% standard deviation of the maximum power signal value. This study highlights a potential security vulnerability in emerging analog CIM accelerators and raises awareness of needed safety features to protect user privacy in such systems.

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Analysis of Power Consumption and Linearity in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs

Cited by 202 publications

References 28 publications

An efficient tool for the assisted design of SAR ADCs capacitive DACs

An efficient tool for the assisted design of SAR ADCs capacitive DACs

Optimal Weight‐Splitting in Resistive Random Access Memory‐Based Computing‐in‐Memory Macros

PowerGAN: A Machine Learning Approach for Power Side‐Channel Attack on Compute‐in‐Memory Accelerators

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