Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm

Cantin, M.-A.; Blaguiere, Y.; Sarvaria, Y.; Lavoie, P.; Granger, Éric

doi:10.1109/iscas.2000.856016

Cited by 5 publications

(6 citation statements)

References 8 publications

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“…Verification is done by comparison to the output of the original software using a representative dataset. The problem of floating-point to fixed point conversion is widely covered and there are various tools addressing this problem [9,12,13,16,36,37,38,68]. Performing the fixed point conversion at early design stages enables much larger acceleration structures, improves performance model precision and avoids complex debugging of numerical problems in hardware.…”

Section: Software Modelmentioning

confidence: 99%

“…S X represents the size of one input channel, S Z the size of one output channel, and n P E the number of PEs and therefore output channels processed in parallel. The boundary can be estimated as shown in Equation (12), where the efficiency will be very high, since all memory accesses are linear and most of them will use the maximum number of bursts,…”

Section: Estimating On Chip Memorymentioning

confidence: 99%

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On Predictable Reconfigurable System Design

Voss

Kwaadgras

Mencer

et al. 2021

ACM Trans. Archit. Code Optim.

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We propose a design methodology to facilitate rigorous development of complex applications targeting reconfigurable hardware. Our methodology relies on analytical estimation of system performance and area utilisation for a given specific application and a particular system instance consisting of a controlflow machine working in conjunction with one or more reconfigurable dataflow accelerators. The targeted application is carefully analyzed, and the parts identified for hardware acceleration are reimplemented as a set of representative software models. Next, with the results of the application analysis, a suitable system architecture is devised and its performance is evaluated to determine bottlenecks, allowing predictable design. The architecture is iteratively refined, until the final version satisfying the specification requirements in terms of performance and required hardware area is obtained. We validate the presented methodology using a widely accepted convolutional neural network (VGG-16) and an important HPC application (BQCD). In both cases, our methodology relieved and alleviated all system bottlenecks before the hardware implementation was started. As a result the architectures were implemented first time right, achieving state-of-the-art performance within 15% of our modelling estimations.

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Section: Software Modelmentioning

confidence: 99%

Section: Estimating On Chip Memorymentioning

confidence: 99%

On Predictable Reconfigurable System Design

Voss

Kwaadgras

Mencer

et al. 2021

ACM Trans. Archit. Code Optim.

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show abstract

“…For this reason, research has emerged aimed at reducing the time and effort spent on this process through design automation. Some research has been targeted at specific applications [7][8][9][10], while others have been targeted at particular hardware architectures [11]. Commercial software, such as MATLAB, provides a toolbox that can help designers with the development of fixed-point design [12].…”

Section: Introductionmentioning

confidence: 99%

A java simulation tool for fixed-point system design

Wijaya¹,

Cantoni²

2009

Proceedings of the Second International ICST Conference on Simulation Tools and Techniques

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The realisation of signal processing algorithms in fixed-point offers performance advantages over floating-point realisations. However, the task is widely acknowledged to be tedious, error prone, and time consuming. In this paper, we propose a systematic approach to automate fixed-point system design. The technique generates fixed-point parameters that satisfy a precision constraint imposed on the primary output of the algorithm to be realised. The development of a simulation framework based on this analysis allows fixed-point designs to be generated in a shorter time frame. The effectiveness of the approach and framework is demonstrated through the implementation of an Erbium-Doped Fibre Amplifier (EDFA) control algorithm in fixed-point.

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“…In the last 10 years, several techniques have been proposed to translate floating-point formulations into fixed-point formulations, especially for specific DSP applications [3][4] [6]. Heuristic …”

Section: Related Workmentioning

confidence: 99%

“…In some complex designs, half of the design time can be spent determining word lengths [2]. Moreover, many algorithms require a careful selection of word lengths to preserve their stability [3]. Therefore, powerful automatic word-length determination methods are required.…”

Section: Introductionmentioning

confidence: 99%

An automatic word length determination method

Cantin

Savaria

Prodanos

et al.

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

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-Automatic word length determination of hardware data paths may require considering several error models, user specifications and hardware costs. A new automatic method for determining the word length of hardware data paths that consider these requirements is proposed and analyzed. The search-based method uses a C/C++ fixed-point simulation tool to model the impact of finite word lengths on overall accuracy. By computing dissimilarities between fixed-point and floating-point simulation results, a procedure searches for a combination of word lengths that meets accuracy criteria specified by the designer. This method is presented with four novel maximization procedures. These four automatic procedures are compared with other procedures given in the literature and adapted into the method. The comparison helps to select a procedure that finds a combination of word lengths that meet user specifications, in a small number of iterations. The procedures are characterized and compared using a dozen DSP algorithms.

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Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm

Cited by 5 publications

References 8 publications

On Predictable Reconfigurable System Design

On Predictable Reconfigurable System Design

A java simulation tool for fixed-point system design

An automatic word length determination method

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