Analysis of read speed latency in 6T‐SRAM cell using multi‐layered graphene nanoribbon and cu based nano‐interconnects for high performance memory circuit design

Abstract

In this study, we designed a 6T‐SRAM cell using 16‐nm CMOS process and analyzed the performance in terms of read‐speed latency. The temperature‐dependent Cu and multilayered graphene nanoribbon (MLGNR)‐based nano‐interconnect materials is used throughout the circuit (primarily bit/bit‐bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano‐interconnects with different interconnect lengths (from 10 μm to 100 μm), for reading‐0 and reading‐1 operations. To execute the reading operation, the CMOS technology, that is, the16‐nm PTM‐HPC model, and the16‐nm interconnect technology, that is, ITRS‐13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high‐speed memories using different nano‐interconnect materials.