Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation

Kong, Weiran; Parries, P.; Wang, G.; Iyer, Subramanian S.

doi:10.1109/test.2008.4700556

Cited by 28 publications

(31 citation statements)

References 12 publications

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“…From [17], at 65nm technology, we get C = 20 f F, L = W = 100 nm, V t = 0.65 V and S t = 112 mV /dec. Substituting these values in Eq.…”

Section: Edram Cell Retention Timementioning

confidence: 99%

“…Let C be the storage capacitance, W and L the width and length of the access transistor, V the voltage applied to the gate of the access transistor, S t the subthreshold slope (defined below), I o f f the off drain current through the access transistor, and T ret the retention time of the eDRAM cell. T ret is defined as the time until the capacitor loses 6/10th of the stored charge [17], that is,…”

Section: Edram Cell Retention Timementioning

confidence: 99%

“…The definition varies from foundry to foundry, and across technology nodes. Kong et al [17] define it as the gate voltage at which the current becomes the expression on the right in Eq. 2.…”

Section: Edram Cell Retention Timementioning

confidence: 99%

“…Since eDRAM refresh is an important problem, there is significant work trying to understand the characteristics of eDRAM charge retention (e.g., [11,16,17]). Recent experimental work from IBM has shown that the retention time of an eDRAM cell strongly depends on the threshold voltage (V t ) of its access transistor [17].…”

Section: Introductionmentioning

confidence: 99%

“…Recent experimental work from IBM has shown that the retention time of an eDRAM cell strongly depends on the threshold voltage (V t ) of its access transistor [17].…”

Section: Introductionmentioning

confidence: 99%

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Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules

Agrawal

Ansari

Torrellas

2014

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)

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EDRAM cells require periodic refresh, which ends up consuming substantial energy for large last-level caches. In practice, it is well known that different eDRAM cells can exhibit very different charge-retention properties. Unfortunately, current systems pessimistically assume worst-case retention times, and end up refreshing all the cells at a conservatively-high rate. In this paper, we propose an alternative approach. We use known facts about the factors that determine the retention properties of cells to build a new model of eDRAM retention times. The model is called Mosaic. The model shows that the retention times of cells in large eDRAM modules exhibit spatial correlation. Therefore, we logically divide the eDRAM module into regions or tiles, profile the retention properties of each tile, and program their refresh requirements in small counters in the cache controller. With this architecture, also called Mosaic, we refresh each tile at a different rate. The result is a 20x reduction in the number of refreshes in large eDRAM modules -practically eliminating refresh as a source of energy consumption.

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“…From [17], at 65nm technology, we get C = 20 f F, L = W = 100 nm, V t = 0.65 V and S t = 112 mV /dec. Substituting these values in Eq.…”

Section: Edram Cell Retention Timementioning

confidence: 99%

Section: Edram Cell Retention Timementioning

confidence: 99%

Section: Edram Cell Retention Timementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…Recent experimental work from IBM has shown that the retention time of an eDRAM cell strongly depends on the threshold voltage (V t ) of its access transistor [17].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations