“…The thermal resistance is known to increase as the gate length is reduced because the smaller cross-sectional area of the MOSFET reduces the heat conduction efficiency to the Si substrate [27]. The strained layer thickness also affects the thermal resistance since the typical strained Si thickness is much lower than the room temperature phonon mean free path (200 nm to 300 nm at 300 K in Si) and phonon scattering at the Si/SiGe heterointerface will contribute to the thermal resistance [27]. Other parameters such as the source/drain extension and the sidewall spacer width will also affect the thermal resistance.…”
Section: Electrical Results and Discussionmentioning
“…The thermal resistance is known to increase as the gate length is reduced because the smaller cross-sectional area of the MOSFET reduces the heat conduction efficiency to the Si substrate [27]. The strained layer thickness also affects the thermal resistance since the typical strained Si thickness is much lower than the room temperature phonon mean free path (200 nm to 300 nm at 300 K in Si) and phonon scattering at the Si/SiGe heterointerface will contribute to the thermal resistance [27]. Other parameters such as the source/drain extension and the sidewall spacer width will also affect the thermal resistance.…”
Section: Electrical Results and Discussionmentioning
“…Simulation results shows SHE degrades on-state current of SOI FinFET but has less impact on BOI device for gate bias greater than 0.6 V [1]. However, for low voltage applications, SHE has minimal influence on both devices [4]. The transient simulation results in Fig.…”
Section: Comparison Of Silicon-on-insulator and Body-on-insulator Finmentioning
“…Since the drain current and power density is higher in short channel devices, self-heating increases as the channel length is reduced. Short channel devices also have higher thermal resistances because the smaller cross-sectional area constricts heat flow away from the channel [7]. The magnitude of the temperature rise in the strained Si channel layer will increase with the thickness of the SiGe SRB since the efficiency of heat dissipation into the Si substrate will reduce with increasing spacing between the heat source (Si channel) and the heat sink (Si substrate).…”
Section: Abstract-the Impact Of Self Heating In Strained Simentioning
confidence: 99%
“…In the J.E approach, the heat generated from current flow is calculated by taking the dot product of the electric field, E, and current density, J (J.E) [7]. The total heat generated in the MOSFET is the sum of the heat generated from Joule heating and that from non-radiative electron-hole generation and recombination processes [20].…”
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