Analysis of single-event upsets in a Microsemi ProAsic3E FPGA

Villa, Paulo Ricardo Cechelero; Goerl, Roger; Vargas, F.; Poehls, Leticia Bolzani; Medina, N. H.; Added, N.; Aguiar, Vitor A. P.; Macchione, Eduardo Luiz Augusto; Aguirre, Fernando; Silveira, M. A. G.; Bezerra, Eduardo Augusto

doi:10.1109/latw.2017.7906772

Cited by 13 publications

(2 citation statements)

References 7 publications

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“…For that reason, the FPGA hardware is flash-based, in our case the Microsemi ProASIC3e FPGA [34]. In this type of FPGA, the configuration memory is not affected by SEUs [52].…”

Section: Fig 5 Checkpoint Recovery Technique Scenariomentioning

confidence: 99%

Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy

et al. 2019

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Embedded soft-core processors are becoming the usual solution to deal with network and data communications inside FPGAs. However, when developing space-based applications, the designer must consider the effects of ionizing radiation such as Total Ionizing Dose (TID) and Single-Event Effect (SEE). The majority of techniques for mitigation of Single-Event Upsets (SEUs) on FPGAs are based on hardware spatial-redundancy. This work presents a fault-tolerance technique, based on the concept of temporal redundancy, with checkpoints and recovery for soft-core processors. The proposed modified architecture is aimed at embedded systems for space applications based on FPGAs. Our experimental results show that the Checkpoint Recovery technique is a valid alternative to traditional spatial-redundancy, especially when considering limited logic area and power budget present on a satellite. The results present levels of reliability comparable to those of the more conventional fault-tolerance techniques. Additionally, the proposed approach does not require modifications of the software source code or compiler.

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“…For that reason, the FPGA hardware is flash-based, in our case the Microsemi ProASIC3e FPGA [34]. In this type of FPGA, the configuration memory is not affected by SEUs [52].…”

Section: Fig 5 Checkpoint Recovery Technique Scenariomentioning

confidence: 99%

Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy

et al. 2019

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show abstract

“…The inconvenience of radiation applications is that most of the time, special designs or components modifications are required to bear certain ionising radiation doses and/or mitigate SEE errors [10], [154], [155], for example using Rad-Hard components. However, it is unusual to find COTS with specific radiation tolerant or resistance properties, and the inconvenience of non-COTS components is that they have a high cost and low availability, in addition to complex political and commercial treaties in some cases [156]. Sometimes this specific Rad-Hard technology can be limited and backward compared to COTS technology [146]; due to the constantly changing and evolving of COTS.…”

Section: Introductionmentioning

confidence: 99%