Analysis of Standard-MOS and Ultra-Low-Power Diodes Composed by SOI UTBB Transistors

Abstract

The main objective of this work is to present an analysis of the performance of Ultra-Thin-Body and Buried Oxide transistors working as Ultra-Low-Power and standard-nMOS diodes. The implementation of different ground planes and substrate biases is analyzed. It is shown a reduced leakage current and increased ratio between the on and off-state currents for both systems with the nMOS devices' substrate biased at -2V. The standard-nMOS shows a reduced leakage current and increased ratio between the on and off-state currents with the substrate bias at -2 V and with a P-type ground plane implemented while the Ultra-Low-Power presents only a significative influence of the ground planes on the ratio between the on and off-state currents. The ground planes do not provoke a significant change in the leakage current, but a noticeable variation can be observed in the ratio between the on and off-state currents due to the higher threshold voltage in relation to the system without ground plane.

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“…In UTBB technology, the silicon layer ( T Si ) has a thickness of around 10 to 20 nm, and the buried oxide (BOX) layer has a thickness of between 10 and 25 nm, featuring improved capacitive coupling of the structure and allowing the biasing of individual devices [8, 9], which can be adjusted to bias the silicon layer in the desired regime to improve device efficiency [10]. These characteristics are often used to improve the performance of UTBB transistors in low‐power analog devices [11] and ultra‐low‐power (ULP) systems [12]. The effect of back biasing can be improved by incorporating a highly doped layer under the BOX to produce a so‐called ground plane (GP) [13, 14].…”