Analysis of strong-arm comparator with auxiliary pair for offset calibration

Li, Shuowei; Xu, Zule; Iizuka, Tetsuya

doi:10.1007/s10470-022-01992-6

Cited by 2 publications

(1 citation statement)

References 13 publications

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“…V CK =high. With these connections, the MOS switches M S1 , M S2 , M S3 and M S4 are off and the charged voltage gets discharged through M 7 , while M 1 and M 2 are conducting [14]- [16]. Transistors M 1 and M 2 are biased by a constant common mode voltage (V CM ).…”

Section: Introductionmentioning

confidence: 99%

An Enhanced Strong ARM Comparator Circuit for Analog to Digital Converter Architectures

Adhithya

2024

IJRASET

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Technological innovations in the current century period have motivated professionals to make electronic gadgets smarter. These advancements are progressing at a brisk pace, facilitating faster changes and increase in computing power. Various technologies such as virtual reality, augmented reality, mobile internet, artificial intelligence, cloud computing, biometric devices, 3D printing machines, genomics, quantum computing, block-chain, industrial automation and robotics. In all these technologies, communications with nearby devices play a major role in its effective functioning. The demand for realizing a smart and better usage experience puts forth strict requirements on the design aspects of next-generation high speed low power CMOS receiver design. One of the major modules in the implementation of high speed low power CMOS receiver device is the analog to digital converter (ADC) architecture. In the process of conversion from analog to digital signals, Quantization and sampling operations are vital and are realized using comparator circuits. The comparator design has a significant role in the design of data converter architecture. Several comparator architectures exist, but StrongARM topology is discussed and implemented in this work due to its negligible static power dissipation and rail to rail output voltages. The proposed novel comparator architecture is designed and simulated in 180nm CMOS process using Cadence Virtuoso tool and operated at supply voltage of VDD=1.8V, a clock frequency of 50MHz

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Section: Introductionmentioning

confidence: 99%

An Enhanced Strong ARM Comparator Circuit for Analog to Digital Converter Architectures

Adhithya

2024

IJRASET

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A Three-Stage Dynamic Comparator for SAR ADC Optimized for Reduced Kickback Noise and Ultra-Low Delay

Sharma,

Rajagopal,

Sekhar

et al. 2024

J CIRCUIT SYST COMP

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This paper presents a novel footless single clock-phase three-stage comparator with internally generated regenerative voltage signals for low kickback noise and high speed. The preamplifier and clocked latch topology of dynamic comparators are considered in this brief. The proposed design has been compared by analyzing and optimizing three state-of-the-art comparator designs: Modified StrongARM, Miyahara’s and Three-Stage. These designs are simulated using the 40[Formula: see text]nm CMOS technology process. The area of the proposed comparator is 28.025[Formula: see text][Formula: see text]m2. When simulated in the SPICE-based simulator HSPICE, under typical performance conditions of 0.9[Formula: see text]V supply voltage, 25∘C, 1 GHz operational frequency, typical process corner (tt), and 1[Formula: see text]mV differential voltage, the proposed comparator produces the best post-layout results, with a minimum delay of 59.9[Formula: see text]ps from meta-stability analysis, energy per comparison of 0.175[Formula: see text]pJ/comparison and a kickback noise of 44.55 [Formula: see text]A. The proposed design also shows a significant improvement in the measured performance parameters over the other state-of-the-art dynamic comparators that have been discussed in this brief. The obtained results show that the proposed comparator is appropriate for 12-bit Successive Approximation Resister Analog-to-Digital Converters (SAR-ADCs) in IoT applications.

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Analysis of strong-arm comparator with auxiliary pair for offset calibration

Cited by 2 publications

References 13 publications

An Enhanced Strong ARM Comparator Circuit for Analog to Digital Converter Architectures

An Enhanced Strong ARM Comparator Circuit for Analog to Digital Converter Architectures

A Three-Stage Dynamic Comparator for SAR ADC Optimized for Reduced Kickback Noise and Ultra-Low Delay

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