Analysis of Temperature Effect in Quadruple Gate Nano-scale FinFET

Toan, Ho Le Minh; Singh, Sruti Suvadarsini; Maity, Subir Kumar

doi:10.1007/s12633-020-00615-x

Cited by 5 publications

(1 citation statement)

References 37 publications

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“…Ho Le Minh Toan et al [71] have proposed quadruple gate FinFET and demonstrated various temperature variation performances. It is reported that a device with a low temperature has shown an improvement in SS and DIBL.…”

Section: Non-ideal Effects On Finfetmentioning

confidence: 99%

FinFET to GAA MBCFET: A Review and Insights

Das,

Rajalekshmi,

James

2024

IEEE Access

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This review article presents a journey from Fin-shaped field effect transistor (FinFET) to gate-all-around multi-bridge channel field effect transistor (GAA MBCFET) technology, unraveling the evolution of semiconductor architectures. This article provides a concise yet insightful overview of the development of FinFET, exploring modified architectures, current trends, and associated constraints. The growing importance of other semiconductor materials instead of Si in FinFET or other technologies has been studied in detail. The article explores an emerging technology called 'GAA MBCFET', highlighting its advantages over FinFET. It also delves into the notable drawbacks and complex fabrication challenges associated with the upcoming GAA MBCFET technology. INDEX TERMS Gate-All-Around (GAA), Multi-Bridge Channel (MBC), Silicon on Insulator (SOI)

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Section: Non-ideal Effects On Finfetmentioning

confidence: 99%

FinFET to GAA MBCFET: A Review and Insights

Das,

Rajalekshmi,

James

2024

IEEE Access

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Impact of gate dielectric on overall electrical performance of Quadruple gate FinFET

Toan

Goswami

2022

Appl. Phys. A

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Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters

Neelam

Prithvi

2022

Silicon

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Nanosheet Field Effect Transistor (NSFET) is a viable contender for future scaling in sub-7-nm technology. This paper provides insights into the variations of DC FOMs for different geometrical con gurations of the NSFET. In this script, DC performance of 3D GAA NSFET is analyzed by varying the width, thickness of the device. Moreover, the gate length is scaled from 20 nm to 5 nm to check for the device suitability in logic applications. The thickness and width of each nanosheet are varied in the range of 5 to 9 nm, and 10 to 50 nm respectively to analyse the performance dependency on the geometry of the device. The impact of geometry of NSFET on various DC performance metrics like transfer characteristics, sub-threshold swing (SS), on current (I ON ), off current (I OFF ), switching ratio (I ON /I OFF ), threshold voltage (V th ) and drain induced barrier lowering (DIBL) are studied. On top of that, the device's electrical characteristics are analyzed for a wide range of temperatures from -43 o C to 127 o C to identify the temperature compensation point and is observed at V GS = 0.55 V and I D = 3.86 × 10 −6 A. Furthermore, the important process parameter, work function variations on transfer characteristics of the device is analyzed. Moreover, the analyses tell that, for sub -7 nm, the NSFET is a potential device for high performance and good logic applications.

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Analysis of Temperature Effect in Quadruple Gate Nano-scale FinFET

Cited by 5 publications

References 37 publications

FinFET to GAA MBCFET: A Review and Insights

FinFET to GAA MBCFET: A Review and Insights

Impact of gate dielectric on overall electrical performance of Quadruple gate FinFET

Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters

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