Analysis of the Back-Gate Effect on the On-State Breakdown Voltage of Smartpower SOI Devices

Schwantes, S.; Fiirthaler, J.; Schauwecker, B.; Dietz, F.; Gräf, M.; Dudek, V.

doi:10.1109/relphy.2006.251241

Cited by 2 publications

(1 citation statement)

References 9 publications

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“…As a result, a typical bell-shaped curve is obtained in the R-PLUDMOS structure where two different regions can be clearly distinguished delimited by the V BR peak value [19] obtained at HWV of 0 V: the RESURF region at negative HWV, and the fully depleted region at positive HWV values. However, in the case of the optimal PLUDMOS, we can see an almost triangular curve which clearly differs from the R-PLUDMOS results when HWV is positive.…”

Section: Br Versus Hwv Comparison In Pludmos and R-pludmos Structuresmentioning

confidence: 89%

Design and optimization of different P-channel LUDMOS architectures on a 0.18 µm SOI-CMOS technology

Cortés¹,

Toulon²,

Morancho³

et al. 2011

Semicond. Sci. Technol.

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This paper focuses on the design and optimization of different power P-channel LDMOS transistors (V BR > 120 V) to be integrated in a new generation of smart-power technology based upon a 0.18 μm SOI-CMOS technology. Different drift architectures have been envisaged in this work with the purpose of optimizing the transistor static (R on-sp /V BR trade-off) and dynamic (R on × Q g ) characteristics to improve their switching performance. Conventional single-RESURF P-channel LUDMOS architectures on thin-SOI substrates show very poor R on-sp /V BR trade-off due to their low RESURF effectiveness. Alternative drift configurations such as the addition of an N-type buried layer deep inside the SOI layer or the application of the superjunction concept by alternatively placing stacked P-and N-type pillars could highly improve the RESURF effectiveness and the P-channel device switching performance.

show abstract

Section: Br Versus Hwv Comparison In Pludmos and R-pludmos Structuresmentioning

confidence: 89%

Design and optimization of different P-channel LUDMOS architectures on a 0.18 µm SOI-CMOS technology

Cortés¹,

Toulon²,

Morancho³

et al. 2011

Semicond. Sci. Technol.

View full text Add to dashboard Cite

show abstract

Design and optimization of high voltage LDMOS transistors on 0.18μm SOI CMOS technology

Toulon

Cortés

Morancho

et al. 2011

Solid-State Electronics

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Analysis of the Back-Gate Effect on the On-State Breakdown Voltage of Smartpower SOI Devices

Cited by 2 publications

References 9 publications

Design and optimization of different P-channel LUDMOS architectures on a 0.18 µm SOI-CMOS technology

Design and optimization of different P-channel LUDMOS architectures on a 0.18 µm SOI-CMOS technology

Design and optimization of high voltage LDMOS transistors on 0.18μm SOI CMOS technology

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