Analysis of the Impact of Wire Resistance on Nano-scale Memristor Crossbar Array Implementing Perceptron Neural Network

Abstract

In this work, the impact of wire resistance in pure memristor crossbar array is mathematically analysed and verified by the circuit simulation. The memristor crossbar without CMOS device is utilized for application of character image recognition, in which wire resistance is presented. Memristor crossbar circuit is analysed separately with respect to wire resistance on vertical line and wire resistance on horizontal line. The result shows that wire resistance on vertical line can be eliminated because they can be self-compensated. The simulation result agrees with the analysis. The variation of output voltage caused by wire resistance less affect the recognition rate of memristor circuit. On the other hand, when wire resistance on horizontal line is assumed to be 2.5Ω. The output voltages are varied remarkably. Such variation of output voltage degrades the recognition rate of memristor crossbar circuit. The interesting phenomenon is also investigated. The column that is close to the first column has less variation of output voltage, whereas the one that is far from the first column has much variation of output voltage. The result can be used in improving the memristor crossbar architecture, which can tolerate the impact of wire resistance. For example, if we want to increase the size of crossbar, we should increase the number of rows, rather than the number of columns.