Analysis of Thin Thermal Oxides on (0001) SiC Epitaxial Layers

Woerle, Judith; Camarda, Massimo; Schneider, Claudia; Sigg, H.; Großner, Ulrike; Gobrecht, J.

doi:10.4028/www.scientific.net/msf.897.119

Cited by 2 publications

(2 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The decrease of defects with the oxide thickness is consistent with what observed in ref. [11] suggesting a deterioration of the interface at the initial stage of the growth in the case of low temperature (1050°C) thermal oxidations in dry oxygen.…”

Section: Resultsmentioning

confidence: 99%

Analysis of 4H-SiC MOS Capacitors on Macro-Stepped Surfaces

Camarda

Woerle

Soulière

et al. 2017

MSF

Self Cite

View full text Add to dashboard Cite

In this study, we compare the electrical properties of MOS capacitors fabricated on different surface morphologies. Comparing a standard, low-roughness (<1nm), surface with one with a roughness of ~40nm, characterized by big macrosteps and large terraces. We compared the two surfaces for different thermal oxide thicknesses, ranging from dOx = 3.6 nm to dOx = 32 nm. The extracted interface state traps (Dit) shows a small, but systematic, decrease of ~10-15 % for the samples with macrosteps.

show abstract

Section: Resultsmentioning

confidence: 99%

Analysis of 4H-SiC MOS Capacitors on Macro-Stepped Surfaces

Camarda

Woerle

Soulière

et al. 2017

MSF

Self Cite

View full text Add to dashboard Cite

show abstract

“…One wafer was steamtreated, one wafer by dry oxidation and the last wafer by nitridation in N 2 O. Dry oxidation was expected to give the worst performance, although there are claims of good performance by growing a thin oxide at 1050 • C [14]. Steamtreatment has been shown to produce PMOS transistors with high mobility (∼15 cm 2 /Vs) [15] and is of interest for SiC CMOS, although the channel electron mobility can be single digit low (∼1 cm 2 /Vs) [16].…”

Section: Experimental Methodsmentioning

confidence: 99%

Ultrafast Pulsed <i>I-V</i> and Charge Pumping Interface Characterization of Low-Voltage <i>n</i>-Channel SiC MOSFETs

Ekström

Malm

Zetterling

2020

MSF

View full text Add to dashboard Cite

Control of defects at or near the MOS interface is paramount for device performance optimization. The SiC MOS system is known to exhibit two types of MOS defects, defects at the SiO2/SiC interface and defects inside of the gate oxide that can trap channel charge carriers. Differentiating these two types can be challenging. In this work, we use several electrical measurement techniques to extract and separate these two types of defects. The charge pumping method and the ultrafast pulsed I-V method are given focus, as they are independent methods for extracting the defects inside the gate oxide. Defects are extracted from low voltage n-channel MOSFETs with differently processed gate oxides: steam-treatment, dry oxidation and nitridation. Ultrafast pulsed I-V and charge pumping gives comparable results. The presented analysis of the electrical characterization methods is of use for SiC MOSFET process development.

show abstract

Analysis of Thin Thermal Oxides on (0001) SiC Epitaxial Layers

Cited by 2 publications

References 11 publications

Analysis of 4H-SiC MOS Capacitors on Macro-Stepped Surfaces

Analysis of 4H-SiC MOS Capacitors on Macro-Stepped Surfaces

Ultrafast Pulsed <i>I-V</i> and Charge Pumping Interface Characterization of Low-Voltage <i>n</i>-Channel SiC MOSFETs

Contact Info

Product

Resources

About