Analysis of threshold voltage instability in AlGaN/GaN MISHEMTs by forward gate voltage stress pulses

Abstract

We report on the investigation of the V th drift behaviour of AlGaN/GaN MISHEMTs upon forward gate voltage stress in dependence of stress bias and stress time. The pulsed measurements allow for the evaluation of the operational regime for optimum device efficiency. We compared the effect of two different high-k gate dielectric materials with similar equivalent oxide thickness e 0 e r /t high-k on the V th instability in order to separate the influence of the heterojunction design and the high-k/GaN-cap interface from the bulk high-k. The matched gate capacitance coupling of the studied Al 2 O 3 and HfO 2 gate dielectric results in an nearly identical critical forward gate voltage, where the AlGaN barrier potential is lowered and severe threshold voltage shift (DV th ) into the positive voltage direction is induced. Beyond this critical forward voltage, detailed time-dependent stress pulse measurements from 1 ms to 1000 s revealed an immediate electron injection and trapping at the oxide/GaN interface for stress pulses with t stress ! 1 ms. The presented results of V th drift analysis demonstrate the limits of the maximum tolerable forward gate voltage of the investigated Al 2 O 3 and HfO 2 MISHEMTs, although the excellent low-leakage currents of the insulated gate would imply a potentially higher gateoverdrive.

(Invited, Digital Presentation) High-κ Gate Oxide Integration and Ohmic Contact Development for AlGaN/GaN MISHEMTs

“…Additionally, the missing conduction band offset reduces spill-over and charge trapping within the GaN capping layer. This reduces the threshold voltage shift and saturation current reduction after gate stress observed for MISHEMTs with Al 2 O 3 as gate dielectric [36].…”

Surface Preconditioning and Postmetallization Anneal Improving Interface Properties and Vth Stability under Positive Gate Bias Stress in AlGaN/GaN MIS‐HEMTs

“…[9][10][11][12][13] In particular, serious V th shift induced by forward gate bias stress due to electron trapping at the dielectric/ III-N interface is one of the major concern in terms of device reliability. [14][15][16][17] Therefore, the minimization of trap states at the interface is a critical issue for GaN-based MIS-HEMTs. Although a reduction of the interface trap density (D it ) has been reported after various surface treatments and postdeposition annealing, [6,[18][19][20][21][22][23][24] still few reports have dealt with the effects of surface and postdeposition treatments in terms of D it and their related implications on V th stability during forward gate bias stress conditions.…”