Analytic Calculation of Jitter Induced by Power and Ground Noise Based on IBIS I/V Curve

Chu, Xiuqin; Hwang, Chulsoon; Fan, Jun; Li, Yushan

doi:10.1109/temc.2017.2725270

Cited by 26 publications

(10 citation statements)

References 12 publications

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“…It is worth noting the perturbation assumption of the P/G voltage, where linear approximation of the I-V functions can be used because the biasing region of the PU and PD transistors of the driver’s last stage will not be severely affected. Therefore, a small-signal transistor model for P/G-induced jitter can be used by including the linear capacitive effects [ 19 ].…”

Section: Proposed Modelling Methodologymentioning

confidence: 99%

“…Moreover, the NN-based behavioral model enables surrogate approximation of nonlinear dynamic function with a good accuracy level. Indeed, the mathematical structure of a dynamic NN approach [ 5 , 17 , 18 , 19 ] has been explored in modeling a nonlinear I/O driver circuit defined by nonlinear differential equations, which is important for transient SPI analysis. For example, NN parametric models based on nonlinear system identification theory have been used to improve IBIS model for the last stage [ 19 ].…”

Section: Problem Formulationmentioning

confidence: 99%

“…Indeed, the mathematical structure of a dynamic NN approach [ 5 , 17 , 18 , 19 ] has been explored in modeling a nonlinear I/O driver circuit defined by nonlinear differential equations, which is important for transient SPI analysis. For example, NN parametric models based on nonlinear system identification theory have been used to improve IBIS model for the last stage [ 19 ]. Furthermore, this modeling methodology accurately approximates the observed nonlinear dynamic memory effects from the identification electrical I/O signals without assuming a predefined equivalent circuit model template.…”

Section: Problem Formulationmentioning

confidence: 99%

See 2 more Smart Citations

Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations

Souilem

Tripathi

Melício

et al. 2021

Sensors

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This paper presents a neural-network based nonlinear behavioral modelling of I/O buffer that accounts for timing distortion introduced by nonlinear switching behavior of the predriver electrical circuit under power and ground supply voltage (PGSV) variations. Model structure and I/O device characterization along with extraction procedure were described. The last stage of the I/O buffer is modelled as nonlinear current-voltage (I-V) and capacitance voltage (C-V) functions capturing the nonlinear dynamic impedances of the pull-up and pull-down transistors. The mathematical model structure of the predriver was derived from the analysis of the large-signal electrical circuit switching behavior. Accordingly, a generic and surrogate multilayer neural network (NN) structure was considered in this work. Timing series data which reflects the nonlinear switching behavior of the multistage predriver’s circuit PGSV variations, were used to train the NN model. The proposed model was implemented in the time-domain solver and validated against the reference transistor level (TL) model and the state-of-the-art input-output buffer information specification (IBIS) behavioral model under different scenarios. The analysis of jitter was performed using the eye diagrams plotted at different metrics values.

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Section: Proposed Modelling Methodologymentioning

confidence: 99%

Section: Problem Formulationmentioning

confidence: 99%

Section: Problem Formulationmentioning

confidence: 99%

See 1 more Smart Citation

Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations

Souilem

Tripathi

Melício

et al. 2021

Sensors

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show abstract

“…Take m = 2 as an example, the previous bit pattern could be ''00'', ''01'', ''10'', and ''11''. Then the response of current logic ''1'' and ''0'' with the previous bit pattern B 2 = 01 is shown as in Fig. 7.…”

Section: A Construct System Response By Mbrmentioning

confidence: 99%

“…As the data rate in high-speed links continuously increases, signal integrity (SI) becomes a challenging problem in realworld applications. Without good SI design, the high-speed links may not function properly [1], [2].…”

Section: Introductionmentioning

confidence: 99%

A Novel Decision Feedback Equalization Structure for Nonlinear High-Speed Links

Chu

Wang

et al. 2020

IEEE Access

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As the degree of nonlinearity in high-speed links becomes more and more serious, traditional decision feedback equalization (DFE) which is based on linear time-invariant assumption can no longer eliminate the inter-symbol interference effectively. In this paper, the shortcomings of traditional DFE structure for nonlinear high-speed links are first analyzed. Then, the multi-bit response (MBR) method is proposed to accurately construct the bit stream responses of the nonlinear high-speed links. Lastly, a novel DFE structure based on the MBR method is presented to improve the signal quality of the nonlinear high-speed links. The accuracy of the proposed method is verified by the simulation based on a nonlinear high-speed link model. Compared with traditional DFE, the proposed DFE structure can significantly improve the signal quality of the nonlinear high-speed links. As the degree of nonlinearity increases, the advantage of the proposed DFE becomes more prominent. INDEX TERMS Decision feedback equalization (DFE), inter-symbol interference (ISI), multi-bit response, nonlinearity, signal integrity.

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A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

et al. 2019

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This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc. INDEX TERMS CMOS inverter, chain of inverters, clock-network, delay-line, I/O, jitter, power supply noise, power supply induced jitter, time interval error, tapered buffer. APPENDIX C FORMULATION OF TRI-DIAGONAL MATRIX FOR EXAMPLE-3

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Analytic Calculation of Jitter Induced by Power and Ground Noise Based on IBIS I/V Curve

Cited by 26 publications

References 12 publications

Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations

Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations

A Novel Decision Feedback Equalization Structure for Nonlinear High-Speed Links

A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

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