Analytical Analysis of Power-Constrained Repeaters’ Insertion in Large-Scale CMOS Chips

Abstract

As the die area of CMOS integrated circuits continues to increase, interconnects will become dominant in determining the performance of the circuits from the standpoint of speed and power consumption. Uniform repeater insertion is an effective method used to reduce the propagation delay of a signal in long resistive-capacitive lines. However, non-optimal repeaters’ insertion yields non-optimal circuit performance. In this work, we provide a mathematical treatment for optimal repeater insertion with power consumption constraints. In particular, a closed-form expression for the optimum number and size of repeaters is given for a two-stage buffer used as a repeater. The validation of the analytical solution is assessed by means of circuit simulations, by comparing the theoretical optimal number and size of the repeaters to be placed in the long resistive-capacitive line with the simulated values.