Analytical behavior of the noise resistance and the noise conductance for a network with parallel and series feedback

Boglione, Luciano; Pollard, R.D.; Postoyalko, V.

doi:10.1109/22.557617

Cited by 11 publications

(7 citation statements)

References 13 publications

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“…Figure 3 shows that the L sopt,1 , at which the LNA noise figure reaches its lowest value, results in X opt,1 = X s = 0 (X s = 0 in the example shown in Fig. 2) as expected from (10). The distance between Z opt,1 (L sopt,1 ) and Z conj,1 (L sopt,1 ) is large, as shown in Fig.…”

Section: Simple Mosfetmentioning

confidence: 70%

“…Since the LNA gain is inversely proportional to L s and if L s , found in (10) or (15), is large then the load noise contribution would be large due to the reduction of the LNA gain. The noise contribution to the noise factor from the load, represented by a noisy resistor R L = 1/G L at a temperature T L (see Fig.…”

Section: Simple Mosfet and A Loadmentioning

confidence: 98%

“…For example, the addition of C gd modifies all noise parameters [10] and makes analysis cumbersome. At the same time, the conjugate of the LNA input impedance is affected by C gd , affecting the optimum L s that minimizes the distance between Z opt and Z Ã in : Note, the noise correlation matrix in (3) is only applicable when C gd is small enough such that |A 0 |(1 and |C 0 -1 |)xL s , and, for accurate location of optimum L s , circuit simulation software is preferred to determine the optimum L s .…”

Section: Lna With Other Small Signal Model Componentsmentioning

confidence: 99%

“…L sopt,1 is determined with ADS computer simulations for the circuit in Fig. 2 and agrees with (10). No reactive matching is applied at the input (X s = 0).…”

Section: Simple Mosfet and A Loadmentioning

confidence: 99%

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Two-port noise figure optimization of source-degenerated cascode CMOS LNAs

Belostotski

Haslett

2008

Analog Integr Circ Sig Process

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This paper presents a noise figure optimization technique for source-degenerated cascode CMOS LNAs with lossy gate inductors. The optimization technique, based on two-port theory, takes into account second order parasitic components. The effect of inductive source degeneration on LNA noise parameters is discussed. Measured noise figures agree well with the simulations confirming the accuracy of the noise model and allowing us to investigate the contributions of various components to the overall noise figure. A 0.18-lm CMOS LNA with an integrated inductor (Q = 7.5) achieves a noise figure of 1.16 dB and a return loss of 20 dB at 1.4 GHz, drawing 39 mA from a 1.8-V voltage supply, having gain (S 21 ) of 14.5 dB, input P1dB of -17.5 dBm, and input IP3 of -13 dBm. LNAs with external inductors having quality factor of Q = 170 and Q = 40 achieve noise figures of 0.65 dB and 0.68 dB and a return loss of 20 dB at 1.4 GHz, drawing 37 mA from a 1.8-V voltage supply, having gain (S 21 ) of 17 dB, input P1dB of -22 dBm, and input IP3 of -14 dBm. The large power consumption of the presented designs was intentionally selected in order to reduce the noise figure, an acceptable trade-off for LNA's targeted for radio telescope applications, and to assess the impact of the large currents flowing through interconnect metals on the noise figure

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Section: Simple Mosfetmentioning

confidence: 70%

Section: Simple Mosfet and A Loadmentioning

confidence: 98%

Section: Lna With Other Small Signal Model Componentsmentioning

confidence: 99%

“…L sopt,1 is determined with ADS computer simulations for the circuit in Fig. 2 and agrees with (10). No reactive matching is applied at the input (X s = 0).…”

Section: Simple Mosfet and A Loadmentioning

confidence: 99%

See 2 more Smart Citations

Two-port noise figure optimization of source-degenerated cascode CMOS LNAs

Belostotski

Haslett

2008

Analog Integr Circ Sig Process

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“…The analysis of feedback amplifiers has finally been carried out [8] and analytical procedures for selecting the series impedance at a given frequency [9], [10] have been devised. These procedures are applicable to any linear two port networks and can be developed for either series or parallel feedback -or both.…”

Section: Introductionmentioning

confidence: 99%

12 GHz MMIC Series Feedback LNA Based on a Novel Analytical Design Procedure for Simultaneous Noise and Power Match

Boglione

Pollard

Postoyalko

1999

29th European Microwave Conference, 1999

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This paper demonstrates a recently developed procedure that is independent of the technology in use as well as of the design frequency. A Low Noise Amplifier (LNA) is designed for simultaneous noise and power match at 12 GHz according to the design procedure [9],[10] and fabricated as a Microwave Monolithic Integrated Circuit (MMIC). Good agreement is achieved between simulated and tested results within the practical constraints related to the research-oriented nature of this work Since the validity of the same technique has already been demonstrated at

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