Analytical derivation of power semiconductor losses in MOSFET multilevel inverters

Gebhardt, Fabian; Vach, Hauke; Fuchs, Friedrich W.

doi:10.1109/epepemc.2012.6397218

Cited by 17 publications

(8 citation statements)

References 11 publications

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“…and switching (P sw. ) power losses of semiconductors in VSMLIs, based on the conductor's static (linear model) characteristics [1,4,5,22,23] are calculated using…”

Section: Calculation Of Power Losses In Vstmlismentioning

confidence: 99%

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Comparison of power losses, current and voltage stresses of semiconductors in voltage source transformerless multilevel inverters

Perantzakis

Christodoulou

Anagnostou

et al. 2014

IET Power Electronics

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The power losses, current and voltage stresses in semiconductor devices in voltage source transformerless multilevel inverters (VSTMLIs) topologies are unequal, depending on the switching states, the duty ratio, the levels of output voltage, the load power factor and the depth of modulation index. Non-uniform power loss profiles mean both unequal junction temperature and power rating in semiconductors. In this study, a comparison of power losses, current and voltage stresses in semiconductors of VSTMLIs is performed. Initially, the structural characteristics and operating principles of dominant VSTMLIs with sinusoidal pulse width modulation are analysed. Then, modifications of existing VSTMLIs and simplified multilevel topologies are proposed, which achieve a further reduction in switch count and power losses in semiconductors. The proposed modified circuitries are suitable for converting existing four-level VSTMLI topologies into five-level ones. This conversion is desirable, when a zero output voltage level under no-load conditions or low modulation indices should be obtained. Power losses in semiconductors are calculated analytically and then confirmed by simulation. A comparative presentation of profiles of power losses, current and voltage stresses in semiconductors of the examined VSTMLIs is analytically carried out. The obtained results are valuable for sizing and selecting the semiconductors in VSTMLIs.

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“…and switching (P sw. ) power losses of semiconductors in VSMLIs, based on the conductor's static (linear model) characteristics [1,4,5,22,23] are calculated using…”

Section: Calculation Of Power Losses In Vstmlismentioning

confidence: 99%

“…New multilevel inverter topologies, based on the active neutral point clamped technique (ANPCT), have been recently developed in order to overcome this problem [1][2][3][4][5]. Using ANPCT, more than one switching strategies are obtained, thus ensuring an improvement of semiconductor's power loss profile.…”

Section: Introductionmentioning

confidence: 99%

Comparison of power losses, current and voltage stresses of semiconductors in voltage source transformerless multilevel inverters

Perantzakis

Christodoulou

Anagnostou

et al. 2014

IET Power Electronics

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“…A number of different methods are available for the calculation of power losses in semiconductor devices. One of the methods available is physics-based, which requires precise models of the power semiconductor devices and circuits under consideration are simulated numerically with the help of specially designed programs [1]. However in this method, the simulation time tend to be very long which doesn't seem to be a practical option for system simulations.. Another widely used approach which has been adopted in this paper, is the behavioral modelling of the power losses in which behaviour of the semiconductor device is captured under different operating conditions which is further used to develop simple equations to model the losses.…”

Section: Introductionmentioning

confidence: 99%

Performance Investigation of Semiconductor Devices using Commutation-speed based methodology for the application of Boost Power Factor Correction

Parkash¹,

Pai²,

Tian³

et al. 2019

Adv. sci. technol. eng. syst. j.

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In this paper, behavioral approach has been adopted for the calculation of total power losses that has been further used to derive an analytical model for the conduction and switching losses in a boost Power Factor Correction (PFC) stage of an On-board Charger (OBC). Detailed investigation of power losses can help in finding out ways to improve efficiency and for this purpose, commutation-speed based methodology has been used to split total power losses into their root causes. This gives opportunity to find the impact that an individual part creates on total losses which can serve as a starting point for efficiency improvement. For the analysis, two devices (IGBT with Si diode and IGBT with SiC diode) are used in the considered topology of PFC and a reduction of 40% was calculated when SiC diode was used instead of Si with the same IGBT. Hence it was found that the implemented method proves to be significantly useful in the optimization of efficiency.

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“…For the losses in multilevel converters, assuming a fixed switching frequency is not correct. In [14] the loss equations for a five-level diode clamped and flying capacitor converter are derived but in a complex way.…”

Section: B Power-losses Calculationsmentioning

confidence: 99%

Evaluation of a dual-T-type converter supplying an open-end winding induction machine

Salem

Belie

Darba

et al. 2013

IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society

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Abstract-The multilevel inverter is a promising technology compared to two-level inverters in the applications of ac-drives and smart-grid applications. In this paper, a dual-T-type threelevel inverters is used to drive an open-end winding induction machine. The Space-Vector Pulse-Width Modulation is selected as a good-performing control strategy to control the dual-inverter. A comparison between the proposed configuration and the conventional diode clamped converter is included. The proposed drive system is designed and modeled by using Matlab/Simulink. It is shown that the converter gives the same hexagon, wave forms and harmonic spectrum of the five level converter. An optimized switching state selection is used to reduce the converter losses. The advantages and drawbacks of the dual-T-type configuration are discussed. In addition, the harmonic analysis and the loss calculations of the dual-T-type converter are provided and compared to the T-type three-level converter and the conventional five-level diode-clamped-converter.

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Analytical derivation of power semiconductor losses in MOSFET multilevel inverters

Cited by 17 publications

References 11 publications

Comparison of power losses, current and voltage stresses of semiconductors in voltage source transformerless multilevel inverters

Comparison of power losses, current and voltage stresses of semiconductors in voltage source transformerless multilevel inverters

Performance Investigation of Semiconductor Devices using Commutation-speed based methodology for the application of Boost Power Factor Correction

Evaluation of a dual-T-type converter supplying an open-end winding induction machine

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