Analytical gate fringe capacitance model for nanoscale MOSFET with layout dependent effect and process variations

Abstract

In this paper, we present an analytical closed model for the gate to source/drain fringing capacitance (Cf) of nanoscale metal oxide semiconductor field effect transistors (MOSFETs), with the consideration of layout dependent effects and process fluctuations. A kind of field-poly structure on shallow trench isolation (STI) is used to separate Cf from other gate-around parasitic capacitances. A significant layout-dependent-effect is found in Cf for the case with high contact density. Based on the device structure, Cf is divided and analytically modeled by three dual-k perpendicular-plate capacitances. The effects of gate to contact space (CPS), contact to contact space (CCS) and the process variations, such as the over-etching of source/drain contact, are taken into account. The proposed model is validated on 40 nm MOSFETs, with a series of layout parameters, and good agreement is obtained between the modeled and measured data over a large range of CPS and CCS. The proposed model can improve the precision for digital and RF circuit simulation in sub-nanometer technology generation.

Mathematical Model and Experimental Design of Nanocomposite Proximity Sensors

“…Although empirical models describing planar capacitive sensor exist, they do not provide actual insight into the interaction of the electric field with the moving object nor do they explain the actual interaction of different parameters in the sensing mechanism. With this in mind, to explore the fringe effect of parasitic capacitance for nanoscale metaloxide-semiconductor field-effect transistor (MOSFETs), several full/semi analytical models have been established by the conformal mapping method [32][33][34][35]. They were also able to estimate, optimize, and compare the fringe capacitance through simulation results without any fitting parameters.…”

Impact of underlap layer on DC and RF/analog performance of asymmetric junctionless dual material double gate MOSFET for low-power analog amplifier design

“…Furthermore, the independent gate operation is also leveraged in JL-MOSFET structures to enhance manufacturing process and enable logical operations without need for traditional junctions [18,19]. Additionally, DG MOSFETs with gate underlap structures is utilized to regulate SCEs with enhancing performance of device for low-power applications [20][21][22][23]. In this regards, various analytical models have been developed to investigate the behaviour of symmetric [24][25][26] or asymmetric [23,24] DG structures, considering the presence of underlap conditions [20][21][22][23].…”

“…Additionally, DG MOSFETs with gate underlap structures is utilized to regulate SCEs with enhancing performance of device for low-power applications [20][21][22][23]. In this regards, various analytical models have been developed to investigate the behaviour of symmetric [24][25][26] or asymmetric [23,24] DG structures, considering the presence of underlap conditions [20][21][22][23].…”