Analytical High-Level Power Model for LUT-Based Components

Abstract

Abstract. This paper presents an extended high-level model for logic power estimation of multipliers and adders implemented in FPGAs in the presence of glitching and correlation. The model is based on an analytical computation of the switching activity produced in the component and the FPGA implementation details of the component structure. It is extended to consider operands of different word-lengths, both zero-mean and nonzero mean signals, and the glitching produced inside the component, taking into account the sign nature of the autocorrelation coefficients of the components' inputs. The number of simulations needed for the model characterization is extremely small and can be reduced to only two. As the final power model is analytical, it is capable of providing power estimates in miliseconds. The results show that the mean relative error is within 10% of low-level power estimates given by the XPower tool.

A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components

“…This model has been further improved in [3] by considering both zero-mean and non-zero mean signals. Next, a brief overview of the approach is given.…”

“…The model has been further extended in order to consider glitching produced inside the component [3]. Although how glitches propagate through logic depends on the logic function they pass through, once again, the fact that the DSP components can be built by repeating one elementary logic block (together with its connections to the neighbouring cells) throughout an array, allows us to make the following assumption.…”

“…The relationship between the switching activity of the MSB and LSB input bits can be deduced from (6) and is expressed as a coefficient l = 1 − ρ [3]. At the same time, this is the relationship we expect between the average glitching produced in the MSB and LSB region, as the amount of glitching is assumed to be proportional to the transition activity of the input bits.…”

“…Another approach used for high-level power estimation is based on the analytical computation of the switching activity of the component and on the implementation details of the components structure [3,4]. The models are precise and parameterizable in terms of input word-lengths and input signal statistics and require a smaller number of lowlevel simulations.…”