Analytical modeling and performance analysis for symmetric double gate stack-oxide junctionless field effect transistor in subthreshold region

Fabiha, Raisa; Saha, Chinmoy Nath; Islam, Md. Shafiqul

doi:10.1109/r10-htc.2017.8288963

Cited by 5 publications

(3 citation statements)

References 11 publications

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“…Designers could also implement stacked-oxide structures. When compared to the conventional architecture, they present higher I on /I o f f , lower SS and DIBL [57,65]. By choosing a high dielectric constant material (e.g., H f O 2 ), a reduction of the leakage current as well as an improvement of the analog parameters could be observed [63,70].…”

Section: Double Gatementioning

confidence: 99%

Junctionless Transistors: State-of-the-Art

2020

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Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as I o n / I o f f , D I B L , and S S , to highlight the advantages and disadvantages of each junctionless transistor category.

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Section: Double Gatementioning

confidence: 99%

Junctionless Transistors: State-of-the-Art

2020

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“…The design and the analysis of the PJLT performed until this point are based on the main assumption of complete depletion. This assumption is often utilized in many scientific articles [17,[24][25][26][27][28][29][30][31][32] to provide a simple analytical formula for the depletion region width in PJLT. This formula represents an approximated model of the depletion region width.…”

Section: Analysis and Simulations Of The Approximated Modelmentioning

confidence: 99%

Analysis of an Approximated Model for the Depletion Region Width of Planar Junctionless Transistors

et al. 2019

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In this paper, we investigate the accuracy of the approximated analytical model currently utilized, by many researchers, to describe the depletion region width in planar junctionless transistors (PJLT). The proposed analysis was supported by numerical simulations performed in COMSOL Multiphysics software. By comparing the numerical results and the approximated analytical model of the depletion region width, we calculated that the model introduces a maximum RMS error equal to 90 % of the donor concentration in the substrate. The maximum error is achieved when the gate voltage approaches the threshold voltage ( V t h ) or when it approaches the flat band voltage ( V F B ) of the transistor. From these results, we concluded that this model cannot be used to determine accurately the flat-band and the threshold voltage of the transistor, although it represents a straightforward method to estimate the depletion region width in PJLT. By using the approximated analytical model, we extracted an analytical formula, which describes the electron concentration at the ideal boundary of the depletion region. This formula approximates the numerical data extracted from COMSOL with a relative error lower than 1 % . The proposed formula is in our opinion, as useful as the formula of the approximated analytical model because it allows for estimating the position of the depletion region also when the drain and source terminals are not grounded. We concluded that the analytical formula proposed at the end of this work could be useful to determine the position of the depletion region boundary in numerical simulations and in graphical representations provided by COMSOL Multiphysics software.

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“…Although a two-dimensional simulation method is used to analyze the shortchannel effect of sub-10 nm DGMOSFETs, a simple analytical model for circuit analysis has the focus of many studies [8][9][10]. However, most analyses using the analytical model are performed on DGMOSFETs of 20 nm or larger [11][12][13]. In this paper, we present an analytical model of the subthreshold swing (SS) that can be applied at 10 nm or less.…”

Section: Introductionmentioning

confidence: 99%

Subthreshold swing model using scale length for sub-10 nm junction-based double-gate MOSFETs

Jung¹

2020

IJECE

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We propose an analytical model for subthreshold swing using scale length for sub-10 nm double gate (DG) MOSFETs. When the order of the calculation for the series type potential distribution is increased it is possible to obtain accuracy, but there is a problem that the calculation becomes large. Using only the first order calculation of potential distribution, we derive the scale length λ1 and use it to obtain an analytical model of subthreshold swing. The findings show this subthreshold swing model is in concordance with a 2D simulation. The relationship between the channel length and silicon thickness, which can analyze the subthreshold swing using λ1, is derived by the relationship between the scale length and the geometric mean of the silicon and oxide thickness. If the silicon thickness and oxide film thickness satisfy the condition of (Lg-0.215)/6.38 > tsi(=tox), it is found that the result of this model agrees with the results using higher order calculations, within a 4% error range.

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Analytical modeling and performance analysis for symmetric double gate stack-oxide junctionless field effect transistor in subthreshold region

Cited by 5 publications

References 11 publications

Junctionless Transistors: State-of-the-Art

Junctionless Transistors: State-of-the-Art

Analysis of an Approximated Model for the Depletion Region Width of Planar Junctionless Transistors

Subthreshold swing model using scale length for sub-10 nm junction-based double-gate MOSFETs

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