The emergence of data-driven technologies including Internet of Things (IoT), artificial intelligence (AI), and cloud computing has led to a surge in data generation and mining. The 3D NAND Flash memory has emerged as a promising technology for handling the big data owing to its ultra-high density, ultra-low cost per bit, fast random access, and multi-level programming capability per cell. However, the conventional punch and plug process used to fabricate the 3D NAND flash memory leads to an inherent tapering of the polysilicon channel of the stacked flash cells. The channel thickness of the flash cells increases monotonically from bottom of the string (common source line, CSL) to the top of the string (bit-line, BL). This results in a nonuniform intrinsic threshold voltage of the flash cells located at different word-line (WL) layers along the string. A non-uniform vertical (Gaussian) channel doping profile was recently proposed to mitigate the impact of channel tapering and realize a uniform threshold voltage distribution. However, an analytical model which may provide a physical insight and can be used for design exploration of 3D NAND flash memory with uniform intrinsic threshold voltage is still elusive. To this end, in this work, for the first time, we formulate an analytical model for the intrinsic threshold voltage and the subthreshold slope of 3D NAND flash cells with a vertical gaussian doping profile in the channel region. The results obtained using the analytical model are in close agreement with the TCAD simulations validating the accuracy of the developed model. We also utilize the analytical model to provide physical insights and necessary design guidelines for further optimizing the performance.