Analytical Modeling of Harmonic Distortions in GAA Junctionless FETs for Reliable Low-Power Applications

Chattopadhyay, Ankush; Chanda, Manash; Bose, Chayanika; Sarkar, Chandan Kumar

doi:10.1007/s11664-021-08999-1

Cited by 4 publications

(3 citation statements)

References 30 publications

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“…In IFM, the direct extraction of HDs from the I d -V g characteristics of the device is easily possible. In this method, a sinusoidal signal of small amplitude (V i ) is added with the DC bias voltage, and the combination of the two is applied at the gate terminal [31,33]. The expressions of HDs are given as [34],…”

Section: Harmonic Distortion Analysis Of C-s-jl-fetmentioning

confidence: 99%

RF, harmonic distortion and linearity analysis of core-shell junctionless-FET using NQS small signal model

Chattopadhyay

2024

Phys. Scr.

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This paper deals with the performance analysis of Core-Shell (C-S) Junctionless (JL) FET structure in the RF domain application. The analysis begins with the non-quasi static (NQS) small signal model representation and from there the extraction of RF-parameters; and there after the harmonic distortions, linearity FOMs and Y-parameter are analyzed in detail. The device is investigated based on the variations of core/shell-thicknesses and shell-dopant concentrations. Y-parameters are evaluated from the NQS small signal model. In the RF domain analysis, the parameters such as, C gs , C gd , R gs , R gd , f T and τ m are assessed to determine its RF merits. Using the two-port equivalent model, the Y-parameters ( Y 11 , Y 12 , Y 21 , Y 22 ) are evaluated and investigated. The second and third order harmonic distortions ( HD 2 , HD 3 ) are calculated using IFM method and studied in detail. In addition to that, second, third harmonic intercept voltages ( VIP 2 , VIP 3 ) and third order intermodulation distortion ( IMD 3 ) are also assessed for its linearity performances in domain specific applications. The proposed device is designed using the Silvaco ATLAS TCAD . The device is calibrated with the experimental data that shows a close match between the two. The proposed device is found to exhibit good linearity and very low harmonic distortion behavior by modulating the shell-doping and thickness.

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Section: Harmonic Distortion Analysis Of C-s-jl-fetmentioning

confidence: 99%

RF, harmonic distortion and linearity analysis of core-shell junctionless-FET using NQS small signal model

Chattopadhyay

2024

Phys. Scr.

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“…1(c Proposed device is analytically modeled, as reported in [28]- [29] with certain geometrical restrictions imposed on the device architecture. They are: i) thickness of the buried oxide layer (t box ) should be greater than or equal to the channel length (L) to reduce interaction between two side gates [29]; ii) channel length should be at least equal to twice of the width/thickness of the device or more, if not less i.e., L ≥ 2W and L ≥ 2t si [30]- [32]. In the perimeterweighted sum approach, channel potential [ψ(x, y, z)] at any point can be expressed as a function of ψ(x, y) and ψ(x, z).…”

Section: Device Structure and Model Descriptionmentioning

confidence: 99%

Performance analysis of dual material junction accumulation mode tri gate junctionless SOI FET: Modeling and Simulation

Goswami

Chattopadhyay²,

Bose

2021

Preprint

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The paper illustrates the performance of Tri-Gate (TG) Dual Material (DM) SOI (Silicon on Insulator) Junctionless (JL) FET operating in Junction Accumulation Mode (JAM). An analytical model is developed to evaluate its performance. The device is also simulated using Silvaco device simulator. Both the analytical and simulation results are compared and found to match closely. Quasi 3-D modeling approach is adopted here to determine the surface potential of the above device. In this technique, the entire 3-D device is segregated into two 2-D devices with certain physical constraints. These 2-D devices are then analyzed separately to obtain the surface potentials, which are added together using suitable multiplication factors to get the surface potential of the 3-D device. This surface potential is, in turn, used to model the threshold voltage, sub-threshold drain current ( I d,sub ) and the drain induced barrier lowering (DIBL). The proposed device configuration reduces the I OFF significantly and offers excellent immunity to SCEs. The response of the proposed device is studied for the variations of certain device parameters, such as, thickness of High- K dielectric layer in stack gate, channel doping, and the workfunctions as well as lengths of the gate metals. Such study will lead to turn the proposed device immune to short channel effects through proper choice of various parameters.

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“…Proposed device is analytically modeled, as reported in [28]- [29] with certain geometrical restrictions imposed on the device architecture. They are: i) thickness of the buried oxide layer (t box ) should be greater than or equal to the channel length (L) to reduce interaction between two side gates [29]; ii) channel length should be at least equal to twice of the width/thickness of the device or more, if not less i.e., L ≥ 2W and L ≥ 2t si [30]- [32]. In the perimeterweighted sum approach, channel potential [ψ(x, y, z)] at any point can be expressed as a function of ψ(x, y) and ψ(x, z).…”

Section: Device Structure and Model Descriptionmentioning

confidence: 99%

Performance Analysis of Dual Material Junction Accumulation Mode tri gate Junctionless SOI FET: Modeling and Simulation

Goswami

Chattopadhyay²,

Bose

2021

Silicon

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Analytical Modeling of Harmonic Distortions in GAA Junctionless FETs for Reliable Low-Power Applications

Cited by 4 publications

References 30 publications

RF, harmonic distortion and linearity analysis of core-shell junctionless-FET using NQS small signal model

RF, harmonic distortion and linearity analysis of core-shell junctionless-FET using NQS small signal model

Performance analysis of dual material junction accumulation mode tri gate junctionless SOI FET: Modeling and Simulation

Performance Analysis of Dual Material Junction Accumulation Mode tri gate Junctionless SOI FET: Modeling and Simulation

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