Analytical Modeling of the Triggering Drain Voltage at the Onset of the Kink Effect for PD SOI NMOS

Sarajlić, Milija; Ramovic, R.

doi:10.1109/icmel.2006.1650964

Cited by 3 publications

(2 citation statements)

References 4 publications

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“…Fig. 4(c) shows the visible kink effect [26], [27] for different heights of the raised body. Kink effect reflects the increase in drain current due to hole accumulation along with the shift in V th .…”

Section: (B)mentioning

confidence: 99%

Raised Body Doping-Less 1T-DRAM With Source/Drain Schottky Contact

Lin

Sun

Lin

et al. 2019

IEEE J. Electron Devices Soc.

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In this paper, we propose a novel structure of doping-less 1T-DRAM with raised body and Schottky contact to source/drain regions which uses thermionic emission to generate electrons and holes. As the device is free from physical doping, the problems associated with random dopant fluctuations will be eliminated in the proposed doping-less topology. Our simulation results show that a programming window of 28.7 μA/μm at a gate length of 10 nm with the retention time of 466 ms at 27 • C and 79 ms at 85 • C can be achieved with the proposed doping-less 1T-DRAM, which is much better than a conventional charge-plasma based doping-less 1T DRAM.

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Section: (B)mentioning

confidence: 99%

Raised Body Doping-Less 1T-DRAM With Source/Drain Schottky Contact

Lin

Sun

Lin

et al. 2019

IEEE J. Electron Devices Soc.

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“…Therefore, the SOl technology provides better performance at radiation environment. There are two types of SOl structures based on the thickness of the top silicon layer: fully depleted transistors (FD) and partially depleted (PD) transistors [2]. PD structures use thicker silicon films and exhibit a floating body isolating the front device from the buried oxide.…”

Section: Introductionmentioning

confidence: 99%

SEU-tolerant active body-bias inverter

Jang

Chang

Kim

et al. 2014

2014 International SoC Design Conference (ISOCC)

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PD-SOI (Partial Depleted Silicon On Insulator) process is a good candidate technology for space system designs, since it features excellent insulation to the silicon substrate compared to the conventional bulk process. However, the radioactive particles from the low earth orbit can causes the single event upset (SEU) or the charge collection in a circuit node, leading to a logical error. We propose SEU-tolerant CMOS logic inverter using a novel active body-bias scheme.

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