Analytical Modeling the Multi-Core Shared Cache Behavior With Considerations of Data-Sharing and Coherence

Abstract

To mitigate the ever worsening "Power wall" and "Memory wall" problems, multi-core architectures with multilevel cache hierarchies have been widely used in modern processors. However, the complexity of the architectures makes the modeling of shared caches extremely complex. In this paper, we propose a data-sharing aware analytical model for estimating the miss rates of the downstream shared cache in a multi-core environment. Moreover, the proposed model can also be integrated with upstream cache analytical models with the consideration of multi-core private cache coherent effects. The integration avoids time-consuming full simulations of the cache architecture, which are required by conventional approaches. We validate our analytical model against gem5 simulation results under 13 applications from PARSEC 2.1 benchmark suites. We compare the L2 cache miss rates with the results from gem5 under 8 hardware configurations including dual-core and quad-core architectures. The average absolute error is less than 2% for all configurations. After integrated with the upstream model, the overall average absolute error is 8.03% in 4 hardware configurations. As an application case of the integrated model, we also evaluate the miss rates of 57 different cache configurations in multi-core and multi-level cache scenarios.

Performance aware shared memory hierarchy model for multicore processors

“…Balasubramonian et al 20 indicated that the memory hierarchy systems that do not meet the applications demands will results in a degradation in the performance of most applications. In 21 , the authors have proposed a data-sharing aware analytical model for estimating the miss rates of multi-level cache hierarchies for multi-core processors. The proposed model can also evaluate coherence misses.…”