Analytical modelling and device design optimisation of epitaxial layer‐based III–V tunnel FET

Abstract

The line tunnelling and heterojunction are two important techniques to improve the performance of the tunnelling field-effect transistors (TFETs). The TFETs that utilise both of these techniques perform superior to the conventional TFETs. The recently proposed T-shaped TFET (TTFET) is one such heterojunction-based line tunnelling device that is expected to become energy efficient switch. For the first time, a physics-based analytical model for surface potential and drain current of epitaxial layer-based heterojunction line TFET has been developed. The model describes the impact of device design parameters on the electrical performance of the device. The Poisson equation is solved with precise boundary conditions to obtain the surface potential model. Kane's model is used to calculate drain current by utilising surface potential model. A good agreement between Synopsys technology computer-aided design simulation and analytical model is observed with 5.4% error in ON current at V GS = V DS = 0.5 V, an average error of 5.80% in surface potential and 7.24% in transconductance. Finally, a device design guideline is presented according to the analytical expressions.

Evaluation of circuit performance of T‐shaped tunnel FET

“…A gate oxide thickness of 3 nm (HfO 2 ) and a metal gate work function of 4.6 eV is used throughout the simulation. The doping concentration of p-type source (InP), n-type drain (In 0.53 Ga 0.47 As), and n-type channel (In 0.53 Ga 0.47 As) is kept at 5 × 10 19 , 5 × 10 18 , and 1 × 10 17 cm −3 , respectively, unless stated otherwise. The width and height (H s ) of the source are set to 12 and 26 nm, respectively.…”

“…In pTTFET structure, the material and dimension of the device are kept same as nTTFET. However, the doping concentrations of the n-type source, p-type drain, and p-type channel are set at 1 × 10 19 , 5 × 10 18 , and 1 × 10 17 cm −3 , respectively, unless stated otherwise. The work function of gate metal in pTTFET device is fixed at 5.0 eV.…”

“…Different TFET structures [12,13] and material systems such as SiGe, III-V semiconductor, two-dimensional-semiconducting materials [14][15][16] have been proposed to improve the performance of TFETs. Recently, an InP/InGaAs heterojunction-based T-shaped TFET (TTFET) structure has been reported [17][18][19] that improves the I ON , ambipolarity, and saturation behaviour of drain current. This validates the potential of TTFETs for digital and analogue applications.…”

Analytical drain current model of strained junctionless nanowire tunnel field‐effect transistor fabricated on virtual substrate

“…The working principle of n‐doped JLNW TFETs is as follows: when the positive gate voltage is applied, the conduction band in the channel region is aligned with the valence band in the source region, forming a tunnelling window at the source/channel interface and allowing carriers to tunnel from the source to the channel region. Thus, this band‐to‐band tunnelling (BTBT) process in JLNW TFETs offers reduced energy consumption and low subthreshold swing that is not limited to 60 mV/dec [6, 7]. Besides, distinct from conventional MOSFETs that are formed by two PN junctions with the doping type of the channel opposite to the source and drain regions, JLNW TFETs have a uniform doping concentration throughout the source, channel and drain regions.…”