Analytical Review of Noise Margin in MVL: Clarification of a Deceptive Matter

Takbiri, Mehdi; Mirzaee, Reza Faghih; Navi, Keivan

doi:10.1007/s00034-019-01063-8

Cited by 29 publications

(24 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The SNM of different designs was detected using the butterfly curve shown in Figs 16 and 17 according to [37]. The SNM is reported as the side of minimum square surrounded in the butterfly curve.…”

Section: Simulation Results and Comparisonsmentioning

confidence: 99%

“…The second drawback is due to the low SNM in the ternary latch (cross‐coupled STIs), as compared to the binary latch. The SNM is the maximum amount of noise voltage that can be applied to the latch node before the stable state is lost [37]. In the binary logic, the maximum noise margin ideal is V DD /2, but in the ternary logic, this value is reduced to V DD /4 [37].…”

Section: Related Workmentioning

confidence: 99%

“…The SNM is the maximum amount of noise voltage that can be applied to the latch node before the stable state is lost [37]. In the binary logic, the maximum noise margin ideal is V DD /2, but in the ternary logic, this value is reduced to V DD /4 [37]. In this paper, two ternary memory cells are designed based on decoding the ternary level to the binary one and saving in two binary latches.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Low storage power and high noise margin ternary memory cells in nanoelectronics

Hosseini

Etezadi

2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

Section: Simulation Results and Comparisonsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Low storage power and high noise margin ternary memory cells in nanoelectronics

Hosseini

Etezadi

2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

“…Finally, noise analysis has also been considered in this paper. However, noise‐tolerant techniques in dynamic circuits [43] and noise margin considerations [44] can further be involved in future works.…”

Section: Discussionmentioning

confidence: 99%

Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source

Azimi

Mirzaee

Navi

et al. 2020

IET Computers & Digital Techniques

Self Cite

View full text Add to dashboard Cite

Every logic style has certain advantages for a specific application. Therefore, it is essential to introduce and investigate different logic styles. Differential cascode voltage switch logic (DCVSL) with the inherent redundancy is known to be an ideal logic style for error detection applications. This study combines ternary static DCVSL (SDCVSL) with dynamic logic (DL) to realise ternary dynamic DCVSL (DDCVSL) by means of a single power source. At first, it is shown that why the same static-to-dynamic conversion method in binary logic fails to operate correctly in ternary logic. Then, two solutions are given. Static power dissipation and switching activity are particularly dealt with in the second proposed ternary DDCVSL to reduce power consumption. The new designs are simulated and tested by using HSPICE simulator and 32 nm Stanford carbon nanotube field effect transistor model. Simulation results and comparisons with a vast range of conventional and state-of-the-art competitors show prominence and great potential for the new ternary circuit methodology. For example, the authors second proposed ternary DDCVSL AND/NAND has 19.7, 37.4, and 60.5% higher performance than some famous static ternary logic styles such as CMOS-like, SDCVSL, and pseudo N-type, respectively, in terms of energy consumption.

show abstract

“…The excessive number of transistors in conventional ternary logic circuits raises a significant energy dissipation and enlarges the chip area. On the other hand, the ternary arithmetic circuits' limited noise margin hampers further downscaling in terms of the supply voltage and the total footprint [25].…”

Section: Introductionmentioning

confidence: 99%