2016
DOI: 10.1587/transfun.e99.a.2463
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Analytical Stability Modeling for CMOS Latches in Low Voltage Operation

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Cited by 4 publications
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“…As a latch circuit used in TDC for ultra-low voltage, we propose to employ a latch circuit using a clocked inverter (CINV latch) [10] shown in Fig. 6.…”
Section: Latch Circuit With Clocked Inverter For Ultra-low Voltagementioning
confidence: 99%
“…As a latch circuit used in TDC for ultra-low voltage, we propose to employ a latch circuit using a clocked inverter (CINV latch) [10] shown in Fig. 6.…”
Section: Latch Circuit With Clocked Inverter For Ultra-low Voltagementioning
confidence: 99%