Analytical study, performance optimisation and design rules for customary static and dynamic subthreshold MOS translinear topologies

Abstract

This paper aims to provide qualitative and quantitative answers to questions related to the impact of transistor-level design parameters upon the performance and accuracy of static and dynamic translinear (TL) circuits in subthreshold CMOS. A methodical, step-by-step, symbolic analysis, exploiting a simplified EKV-based approximation is performed upon customary static TL topologies, including the four MOS transistor (MOST) multiplier/divider, the squarer circuit and the alternating formation of a six MOST multiplier/divider. The logarithmic integrator is treated as a typical dynamic TL analysis example. The produced EKV-based symbolic analysis results are compared against the ideally expected behaviours and Spectre®-BSIM3V3model-simulations. The satisfying agreement between the proposed EKV-based model and Spectre simulator allowed us to proceed further and investigate the conditions under which optimal behaviour is achieved. Optimisation techniques, based on MOSTs' geometrical parameters combinations, resulted in the articulation of practical design rules