Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator

Zhang, Jeff; Gu, Tianyu; Basu, Kanad; Garg, Siddharth

doi:10.1109/vts.2018.8368656

Cited by 136 publications

(95 citation statements)

References 29 publications

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“…(a) Hardware design optimization/enhancements for permanent fault mitigation Figure 6c shows the hardware optimization proposed in [8] for mitigating permanent faults, where an additional multiplexer is inserted in the datapath for bypassing the MAC computation in the PEs in case of faults. The baseline systolic array architecture and the design of the conventional processing element are shown in figures 6a,b, respectively.…”

Section: Salvagednns: a Methodology For Salvaging Dnn Accelerators Usmentioning

confidence: 99%

“…Similarly, in Case 4 (figure 9e) the mapping is defined based on its fault map. It is important to clarify here that, similar to the state-ofthe-art FAP technique [8], our proposed technique also requires adaptation for each faulty chip based on its fault map. However, unlike the state of the art, our technique can avoid retraining, and, therefore requires much less time for the adaptation compared to the retraining-based approaches, as will be shown in §4b(v).…”

Section: (F) Salvagednn Under Changing Fault Mapsmentioning

confidence: 99%

“…Note that these faults can be detected and the fault maps can be obtained by an initial BIST (built-in-selftest) like method [18,19]. Zhang et al in [8] also proposed hardware modifications in which the computations of individual MAC units in a DNN accelerator can be bypassed to support the FAP method. Further, they proposed a Fault-Aware Pruning + Training (FAP+T) method which allows the fine-tuning of a model given the fault map of the hardware.…”

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confidence: 99%

“…illustrates the impact of using SalvageDNN and then applying fault-aware retraining on the accuracy of the VGG11 network for the Cifar10 classification. The subfigures show the comparison between the 'FAP+T'[8] and the 'SalvageDNN + retraining', when the underlying hardware has faulty PEs. As can be seen from thefigure, both the approaches perform equally royalsocietypublishing.org/journal/rsta Phil.…”

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confidence: 99%

“…Execution time comparison of SalvageDNN with retraining-based approach, i.e. FAP+T[8], for different networks trained on different datasets.…”

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confidence: 99%

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SalvageDNN: salvaging deep neural network accelerators with permanent faults through saliency-driven fault-aware mapping

Hanif

Shafique

2019

Phil. Trans. R. Soc. A.

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Deep neural networks (DNNs) have proliferated in most of the application domains that involve data processing, predictive analysis and knowledge inference. Alongside the need for developing highly performance-efficient DNN accelerators, there is an utmost need to improve the yield of the manufacturing process in order to reduce the per unit cost of the DNN accelerators. To this end, we present ‘SalvageDNN’, a methodology to enable reliable execution of DNNs on the hardware accelerators with permanent faults (typically due to imperfect manufacturing processes). It employs a fault-aware mapping of different parts of a given DNN on the hardware accelerator (subjected to faults) by leveraging the saliency of the DNN parameters and the fault map of the underlying processing hardware. We also present novel modifications in a systolic array design to further improve the yield of the accelerators while ensuring reliable DNN execution using ‘SalvageDNN’ and negligible overheads in terms of area, power/energy and performance. This article is part of the theme issue ‘Harmonizing energy-autonomous computing and intelligence’.

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Section: Salvagednns: a Methodology For Salvaging Dnn Accelerators Usmentioning

confidence: 99%

Section: (F) Salvagednn Under Changing Fault Mapsmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

“…Execution time comparison of SalvageDNN with retraining-based approach, i.e. FAP+T[8], for different networks trained on different datasets.…”

mentioning

confidence: 99%

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SalvageDNN: salvaging deep neural network accelerators with permanent faults through saliency-driven fault-aware mapping

Hanif

Shafique

2019

Phil. Trans. R. Soc. A.

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PRTSM: Hardware Data Arrangement Mechanisms for Convolutional Layer Computation on the Systolic Array

Wang¹,

Wang²,

Li³

et al. 2019

Lecture Notes in Computer Science

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The systolic array is an array of processing units which share the inner data flow. Since the 2D systolic array fits the operation of multiplication and accumulation (MAC) naturally, there are many groups which use the systolic array to accelerate the computation of DNN (Deep Neural Network). However, the performance of the systolic array is limited by the data bandwidth. Some groups solve this problem with the method of loop tiling and care little about the pixel reuse potential of the convolutional layer. In this paper, we propose a novel method of PRTSM (Pixels Reuse with Time and Spatial Multiplexing) which reuses the pixels of the input feature map with time and spatial multiplexing. With it, we can significantly reduce the pressure of bandwidth and save the time of data preparing for convolutional layers on the systolic array. We propose three algorithms for this method and implement the corresponding hardware mechanisms on Xilinx FPGA XCVU440. Experiments show that our hardware mechanisms can reduce at least 72.03% of the offchip traffic. The mechanisms proposed by this paper can reach a peak performance of 64.034 GOPS with a frequency of 167M Hz.

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Robust Computing for Machine Learning-Based Systems

Hanif

Khalid

Putra

et al. 2020

Dependable Embedded Systems

Self Cite

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The drive for automation and constant monitoring has led to rapid development in the field of Machine Learning (ML). The high accuracy offered by the state-of-the-art ML algorithms like Deep Neural Networks (DNNs) has paved the way for these algorithms to being used even in the emerging safety-critical applications, e.g., autonomous driving and smart healthcare. However, these applications require assurance about the functionality of the underlying systems/algorithms. Therefore, the robustness of these ML algorithms to different reliability and security threats has to be thoroughly studied and mechanisms/methodologies have to be designed which result in increased inherent resilience of these ML algorithms. Since traditional reliability measures like spatial and temporal redundancy are costly, they may not be feasible for DNN-based ML systems which are already super computer and memory intensive. Hence, new robustness methods for ML systems are required. Towards this, in this chapter, we present our analyses illustrating the impact of different reliability and security vulnerabilities on the accuracy of DNNs. We also discuss techniques that can be employed to design ML algorithms such that they are inherently resilient to reliability and security threats. Towards the end, the chapter provides open research challenges and further research opportunities.

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Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator

Cited by 136 publications

References 29 publications

SalvageDNN: salvaging deep neural network accelerators with permanent faults through saliency-driven fault-aware mapping

SalvageDNN: salvaging deep neural network accelerators with permanent faults through saliency-driven fault-aware mapping

PRTSM: Hardware Data Arrangement Mechanisms for Convolutional Layer Computation on the Systolic Array

Robust Computing for Machine Learning-Based Systems

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