2015
DOI: 10.1016/j.sse.2014.11.007
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Angle dependent conductivity in graphene FET transistors

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“…In Figure 1b, we consider a device design contrasted with a rectangular single layer of silicene that is deposited on the dielectric layer SiO 2$\hskip.001pt 2$ and has two gold contacts for the source and drain, a back gate, and a top gate. [ 31 ] The top gate modifies the current that flows through the device from source to drain, passing over a potential barrier, while the rear gate regulates the charge carrier density of the sample. Since the sample is large enough to not be considered a strip, we assume that there are no edge effects.…”
Section: Theoretical Modelmentioning
confidence: 99%
“…In Figure 1b, we consider a device design contrasted with a rectangular single layer of silicene that is deposited on the dielectric layer SiO 2$\hskip.001pt 2$ and has two gold contacts for the source and drain, a back gate, and a top gate. [ 31 ] The top gate modifies the current that flows through the device from source to drain, passing over a potential barrier, while the rear gate regulates the charge carrier density of the sample. Since the sample is large enough to not be considered a strip, we assume that there are no edge effects.…”
Section: Theoretical Modelmentioning
confidence: 99%