ANMLzoo: a benchmark suite for exploring bottlenecks in automata processing engines and architectures

Wadden, Jack; Dang, Vinh Quang; Brunelle, Nathan; Tracy, Tommy; Guo, Deyuan; Sadredini, Elaheh; Wang, Ke; Bo, Chunkun; Robins, Gabriel; Stan, Mircea R.; Skadron, Kevin

doi:10.1109/iiswc.2016.7581271

Cited by 59 publications

(76 citation statements)

References 17 publications

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“…Custom hardware accelerators [11,12] for FSA can avoid such problems by providing a large memory and having customized optimizations. For instance, Micron Automata Processor (MAP) (based on DRAM technology) [11] stores up to 48k states on a single chip, which is large enough for configuring the automata of most applications including Snort and Protomata [13]. It processes one input symbol in each cycle [11].…”

Section: Introductionmentioning

confidence: 99%

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Time-division Multiplexing Automata Processor

Nguyen

Lebdeh

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Automata Processor (AP) is a special implementation of non-deterministic finite automata that performs pattern matching by exploring parallel state transitions. The implementation typically contains a hierarchical switching network, causing long latency. This paper proposes a methodology to split such a hierarchical switching network into multiple pipelined stages, making it possible to process several input sequences in parallel by using time-division multiplexing. We use a new resistive RAM based AP (instead of known DRAM or SRAM based) to illustrate the potential of our method. The experimental results show that our approach increases the throughput by almost a factor of 2 at a cost of marginal area overhead.

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Section: Introductionmentioning

confidence: 99%

“…For pattern matching applications, this means that all the patterns are matched simultaneously. As a result, these accelerators achieve a much higher throughput as compared with CPU or GPU implementations [12,13]. Unified Automata Processor (UAP) [12] contains multiple cores that are simplified for automata processing.…”

Section: Introductionmentioning

confidence: 99%

Time-division Multiplexing Automata Processor

Nguyen

Lebdeh

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…Synthesizing the ANMLZoo benchmark suite [26] using REAPR for the Xilinx SDAccel platform confirmed the initial hypothesis that FPGAs are well-suited for automata processing; the spatial representation of nondeterministic finite automata naturally maps to the spatial representation of circuit elements in reconfigurable hardware. Thanks to this compatability, FPGAs can offer significant performance and efficiency boosts for automata processing workloads compared to traditional von Neumann computer architectures.…”

Section: Chapter 6 Conclusionmentioning

confidence: 77%

“…We synthesize the ANMLZoo [26] automata benchmark suite developed by Wadden et al to determine the efficiency of REAPR. ANMLZoo contains several applications falling into three broad categories: regular expressions, widgets, and mesh.…”

Section: Benchmarksmentioning

confidence: 99%

FPGA Automata Processing

Xie

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Dwindling inter-generational CPU performance and power consumption improvements previously made possible by semiconductor scaling motivate hardware specialization for a wide variety of tasks. In recent years, implementing certain algorithms as specialized circuits ("accelerators") has been proven to improve both speediness and power/energy efficiency compared to the equivalent CPU implementation. One particular domain that shows great promise for hardware specialization is automata processing. Finite automata are most commonly known as the back-end data structures for regular expressions, which are used in a wide variety of applications such as antivirus file scanning and packet payload inspection for network intrusion detection systems (NIDS). Several research efforts have extended the applicability of finite automata beyond just regular expression into domains such as machine learning, particle physics, bioinformatics, and pattern mining. The versatility of automata processing as well as its inefficiency on traditional von Neumann computer architectures informs the need for a flexible and high-performance accelerator for these applications.In this thesis, an FPGA-based automata processing hardware accelerator is implemented in two different configurations: (1) a traditional discrete FPGA accelerator board attached over PCI-Express; and (2) a new tightly-coupled cache-coherent FPGA accelerator architecture utilizing the Intel Broadwell Xeon CPU + Arria 10 FPGA platform, known as the Hardware Accelerator Research Platform ("HARP").i

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“…To take advantage of this framework, images/image features need to be encoded into regular expressions or loaded onto the AP of its other programming modalities [26,27]. These strings of characters which represent an image or a particular category of images are ultimately encoded as state machines on the automata.…”

Section: Image Similarity Using Multinary Representationmentioning

confidence: 99%

IP on AP: Exploring Image Processing on the Automata Processor

Ly¹

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The Automata Processor is a novel hardware accelerator that can perform pattern matching in parallel. To date, this pattern matching has been limited to one-dimensional problems that can be implemented as flexible string-matching methods such as those found in genomics. In this thesis, we present a novel process of implementing image retrieval using a multinary representation for deployment on an automata framework. Images are encoded into discriminative and unique regular expression descriptors in such a way that can be used for classification purposes. The regular expression descriptors are streamed through sets of non-deterministic finite automata (NFA).To improve performance of this multi-dimensional classification problem, we transform discriminative feature descriptors using a cumulative distribution transform. The transformed features are encoded into regular expressions which can be executed on the automata processor.The thesis also highlights methods of evaluating the similarity between images using these regular expressions in the automata processor. Our image retrieval and classification method improves on classification accuracy and achieves a run-time of less than one one-hundredth of a second per image which represents a three-fold improvement over competing architectures.i ACKNOWLEDGEMENTS

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ANMLzoo: a benchmark suite for exploring bottlenecks in automata processing engines and architectures

Cited by 59 publications

References 17 publications

Time-division Multiplexing Automata Processor

Time-division Multiplexing Automata Processor

FPGA Automata Processing

IP on AP: Exploring Image Processing on the Automata Processor

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