ANN in Hardware with Floating Point and Activation Function Using Hybrid Methods

Sartin, Maicon Aparecido; Silva, Alexandre César Rodrigues da

doi:10.4304/jcp.9.10.2258-2265

Cited by 4 publications

(2 citation statements)

References 13 publications

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“…There is a study that have multiplied matrix using 64-bit floating-point number format [6]. Artificial neural network design with floating point numbers and training of this network are among these applications [7][8][9][10]. A customized single instruction multiple data (SIMD) is designed using a 16-bit floatingpoint number [11].…”

Section: Ieee754 Floating-point Number Formatmentioning

confidence: 99%

Implementation and Design of 32 Bit Floating-Point ALU on a Hybrid FPGA-ARM Platform

Ozkilbac

2019

BEN

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FPGAs have capabilities such as low power consumption, multiple I/O pins, and parallel processing. Because of these capabilities, FPGAs are commonly used in numerous areas that require mathematical computing such as signal processing, artificial neural network design, image processing and filter applications. From the simplest to the most complex, all mathematical applications are based on multiplication, division, subtraction, addition. When calculating, it is often necessary to deal with numbers that are fractional, large or negative. In this study, the Arithmetic Logic Unit (ALU), which uses multiplication, division, addition, subtraction in the form of IEEE754 32-bit floating-point number used to represent fractional and large numbers is designed using FPGA part of the Xilinx Zynq-7000 integrated circuit. The programming language used is VHDL. Then, the ALU designed by the ARM processor part of the same integrated circuit was sent by the commands and controlled.

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Section: Ieee754 Floating-point Number Formatmentioning

confidence: 99%

Implementation and Design of 32 Bit Floating-Point ALU on a Hybrid FPGA-ARM Platform

Ozkilbac

2019

BEN

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“…An intuitive approach is to use Taylor series expansion around origin and is used by [52, 53] at the 4th and 5th order, respectively. In [54, 55] the authors propose two approaches, one composed of a PWL approximation coupled with a RA-LUT and one composed of the PWL approximation with a combinatorial logic circuit. The authors compare the solutions with classic (Alippi, PLAN) PWL approximation focusing on resources required and accuracy degradation.…”

Section: Activation Functions For Fast Computationmentioning

confidence: 99%

On Training Efficiency and Computational Costs of a Feed Forward Neural Network: A Review

Laudani

Lozito

Fulginei

et al. 2015

Computational Intelligence and Neuroscience

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A comprehensive review on the problem of choosing a suitable activation function for the hidden layer of a feed forward neural network has been widely investigated. Since the nonlinear component of a neural network is the main contributor to the network mapping capabilities, the different choices that may lead to enhanced performances, in terms of training, generalization, or computational costs, are analyzed, both in general-purpose and in embedded computing environments. Finally, a strategy to convert a network configuration between different activation functions without altering the network mapping capabilities will be presented.

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Hardware implementation of an artificial neural network model to predict the energy production of a photovoltaic system

Baptista¹,

Rodrigues²,

Travieso-Gonzlez

et al. 2017

Microprocessors and Microsystems

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ANN in Hardware with Floating Point and Activation Function Using Hybrid Methods

Cited by 4 publications

References 13 publications

Implementation and Design of 32 Bit Floating-Point ALU on a Hybrid FPGA-ARM Platform

Implementation and Design of 32 Bit Floating-Point ALU on a Hybrid FPGA-ARM Platform

On Training Efficiency and Computational Costs of a Feed Forward Neural Network: A Review

Hardware implementation of an artificial neural network model to predict the energy production of a photovoltaic system

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