2014 17th Euromicro Conference on Digital System Design 2014
DOI: 10.1109/dsd.2014.91
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Anytime System Level Verification via Random Exhaustive Hardware in the Loop Simulation

Abstract: We present a parallel random exhaustive Hardware In the Loop Simulation based model checker for hybrid systems that, by simulating all operational scenarios exactly once in a uniform random order, is able to provide, at any time during the verification process, an upper bound to the probability that the System Under Verification exhibits an error in a yet-to-besimulated scenario (Omission Probability).We show effectiveness of the proposed approach by presenting experimental results on System Level Formal Verif… Show more

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Cited by 24 publications
(48 citation statements)
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“…The use of continuous-time monitors embedded in the VPH model gives us a flexible way to model both bounded safety and bounded liveness properties (see, e.g., [25,27] for a use of monitors to define safety properties for cyber-physical systems).…”
Section: Modelling Treatment Invariants and Goalsmentioning
confidence: 99%
“…The use of continuous-time monitors embedded in the VPH model gives us a flexible way to model both bounded safety and bounded liveness properties (see, e.g., [25,27] for a use of monitors to define safety properties for cyber-physical systems).…”
Section: Modelling Treatment Invariants and Goalsmentioning
confidence: 99%
“…In [2], [3], [4] a methodology has been presented which allows exhaustive HILS. Such methodology works as follows.…”
Section: A Motivationsmentioning
confidence: 99%
“…Also, sequences of inputs to the SUV are of bounded length, thus the problem addressed is bounded SLFV. Accordingly, in [2], [3], [4], a simulation scenario is a finite sequence of disturbances. A system is expected to withstand all disturbance sequences that may arise in its operational environment.…”
Section: A Motivationsmentioning
confidence: 99%
“…Also, even systems that have been fully verified at design time may be subject to external faults such as those introduced by unexpected hardware failures or human inputs. One way to address this issue is to model nondeterministic behaviours (such as faults) as disturbances, and to verify the system with respect to this disturbance model [29]. However, it may be impossible to model all potential unexpected behavior at design time.…”
Section: Introductionmentioning
confidence: 99%