2002
DOI: 10.1145/581888.581893
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Application-adaptive intelligent cache memory system

Abstract: This article presents the design of a simple hardware-controlled, high performance cache system. The design supports fast access time, optimal utilization of temporal and spatial localities adaptive to given applications, and a simple dynamic fetching mechanism with different fetch sizes. Support for dynamically varying the fetch size makes the cache equally effective for general-purpose as well as multimedia applications. Our cache organization and operational mechanism are especially designed to maximize tem… Show more

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Cited by 5 publications
(2 citation statements)
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“…Pad power can be calculated as 0.5 * Vdd 2 * (0.5 * (Wdata + Waddr)) * 20pF [6], [9], [10], [12], where Wdata and Waddr are the number of bits for both the data sent/returned and the address sent to the lower level memory on a miss request. The last term 20pF is the load capacitance for off-chip destinations [10], [12]. A data cache with a 32-byte block size is assumed, where the values of Wdata and Waddr are also 32 bits.…”
Section: Experimental Methodologymentioning
confidence: 99%
“…Pad power can be calculated as 0.5 * Vdd 2 * (0.5 * (Wdata + Waddr)) * 20pF [6], [9], [10], [12], where Wdata and Waddr are the number of bits for both the data sent/returned and the address sent to the lower level memory on a miss request. The last term 20pF is the load capacitance for off-chip destinations [10], [12]. A data cache with a 32-byte block size is assumed, where the values of Wdata and Waddr are also 32 bits.…”
Section: Experimental Methodologymentioning
confidence: 99%
“…One possible improvement to the native scheme is to dynamically change the block-size during execution. Previous work in this area have shown promising results [16,9,19,27].…”
Section: Proposed Scheme: Dynamic Blocksize Selection and Compressionmentioning
confidence: 99%