Application-based dynamic reconfiguration in optical network-on-chip

Falahati, Hajar; Koohi, Somayyeh; Hessabi, Shaahin

doi:10.1016/j.compeleceng.2015.04.019

Cited by 5 publications

(2 citation statements)

References 19 publications

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“…The drawback of this technique, however, is that it gives less attention to the complexity introduced due to the increased number of reconfigurable regions for each router and the power consumption per single router configuration. Researchers in [4][5][6][7] have proposed run-time reconfigurable topologies to introduce dynamic flexibility to communication needs. Different adaptive routing algorithms have been proposed in [8][9][10][11][12][13][14] for dynamically reconfigurable NoCs that are capable of avoiding deadlock and obstacles by bypassing faulty components.…”

Section: Introductionmentioning

confidence: 99%

Dynamically Scalable NoC Architecture for Implementing Run-Time Reconfigurable Applications

Ijaz,

Kidane,

Bourennane

et al. 2023

Micromachines

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The paper proposes two architectures for a dynamically scalable network-on-chip (NoC) for dynamically reconfigurable intellectual properties (IPs) to save power. The first architecture is a run-time scalable column-based NoC, where the columns of the NoC are scaled up and down at run-time depending on the demands to connect reconfigurable IPs. The second architecture is an extension of the first, where both the rows and columns of the NoC are dynamically scaled up and down on demand. A robust control manager is developed to control the IP and sub-NoC reconfigurations by optimizing the reconfiguration costs. The proposed architectures have been implemented and tested in actual prototypes on a Virtex 6 FPGA mounted on the ML605 board. The results show that dynamically scalable architectures are capable of significant power reduction as compared to traditional static architectures for the same size of the NoC. It is anticipated that the scalable NoC can be very useful for sharing the FPGA resources among IPs at runtime.

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Section: Introductionmentioning

confidence: 99%

Dynamically Scalable NoC Architecture for Implementing Run-Time Reconfigurable Applications

Ijaz,

Kidane,

Bourennane

et al. 2023

Micromachines

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“…The resulting growth of High-Performance Computing (HPC) systems, supercomputers and data centers are increasingly reshaping the network infrastructure and the interconnection network [3], which on the other hand increased the energy consumption and cost budgets [4]. In recent years, Networks-on-Chips (NoCs) have been proposed as a methodology for simplifying and improving the design of Multiprocessor Systems-on-Chips (MPSoC) [5], [6] and [7], 3D architectures [8], routing and mapping algorithms have been proposed [9], [10], [11] and [12], Several reconfigurable ONoCs have been presented [13], [14], [15] and [16] so far. However, they either suffer from considerable area overhead and low efficiency.…”

Section: Introductionmentioning

confidence: 99%

A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

et al. 2021

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Photonic networks and software-defined networks are two promising technologies to improve network-onchips performance, scalability, and resource utilization. Several architectures suffer from scaling limitations, high-power consumption, and noise interference drawbacks. In this paper, an enhanced photonic network-on-chip architecture called (SD-PNoC) is presented. The proposed architecture based on a hybrid hardware-software approach, and a Software-Defined Management Orchestrator (SDMO) to separate the network control and data forwarding planes. This orchestrator has hosted on the upper hardware router as a virtual layer capable of dynamic management. It reconfigures data forwarding paths and allows dynamic execution of different algorithms in real-time, as it scales the proposed topology based on both applications and the network requirements. The proposed SD-PNoC architecture, hierarchical communication protocols, and orchestrator management policies were implemented, simulated, and tested using a customized Phoenix-SIM framework in the OMNIT++ simulation environment. Numerous simulation experiments under different conditions have been performed and have proven that the performance of the proposed architecture is better than that of the conventional electronic network on chip (ENoC). Furthermore, simulation results without using the management policies showed that the latency is reduced by 46% and 25.5% for the 4x4 and 8x8 network structures, respectively. While the power consumption is reduced by 76.5% and 78.5% for the 4x4 and 8x8 network structures, respectively. Besides, the chip area is reduced by 33.4%. Moreover, simulation results of SDMO with using the management policies for the 8x8 network structures increased the enhancement of latency from 25.5% to 37.3% and the power consumption from 78.5% to approximately 80%, which assure the ability of the proposed architecture to remarkably enhance the overall performance of complex network-on-chip structures.

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