Abstract:This paper describes the implementation of a part of the JPEG 2000 algorithm ͑MQ decoder and arithmetic decoder͒ on a fieldprogrammable gate array ͑FPGA͒ board by using dynamic reconfiguration. A comparison between static and dynamic reconfiguration is presented, and new analysis criteria ͑spatiotemporal efficiency, logic cost, and performance time͒ have been defined. The MQ decoder and arithmetic decoder are attractive for dynamic reconfiguration implementation in applications without parallel processing. Thi… Show more
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