Application Experiences with a Real-Time Java Processor

Schoeberl, Martin

doi:10.3182/20080706-5-kr-1001.01575

Cited by 20 publications

(18 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Furthermore, jPapaBench is a Java port of the real-time benchmark PapaBench [27]. JemBench includes two real-world embedded applications [34]: Kfl is one node of a distributed control application and Lift is a lift controller deployed in industrial automation. The Kfl example is a very static application, written in conservative, procedural style.…”

Section: Discussionmentioning

confidence: 99%

Data cache organization for accurate timing analysis

2012

Self Cite

View full text Add to dashboard Cite

Caches are essential to bridge the gap between the high latency main memory and the fast processor pipeline. Standard processor architectures implement two first-level caches to avoid a structural hazard in the pipeline: an instruction cache and a data cache. For tight worst-case execution times it is important to classify memory accesses as either cache hit or cache miss. The addresses of instruction fetches are known statically and static cache hit/miss classification is possible for the instruction cache. The access to data that is cached in the data cache is harder to predict statically. Several different data areas, such as stack, global data, and heap allocated data, share the same cache. Some addresses are known statically, other addresses are only known at runtime. With a standard cache organization all those different data areas must be considered by worst-case execution time analysis. In this paper we propose to split the data cache for the different data areas. Data cache analysis can be performed individually for the different areas. Access to an unknown address in the heap does not destroy the abstract cache state for other data areas. Furthermore, we propose to use a small, highly associative cache for the heap area. We designed and implemented a static analysis for this cache, and integrated it into a worst-case execution time analysis tool.

show abstract

Section: Discussionmentioning

confidence: 99%

Data cache organization for accurate timing analysis

2012

Self Cite

View full text Add to dashboard Cite

show abstract

“…The Java processor JOP, which is the basis of the presented paper, has been used with success to implement several commercial real-time applications [18]. JOP is open-source under the GNU GPL and all design files (including the CMP version), the documentation, and the WCET analysis tool are available at http://www.jopdesign.com/.…”

Section: Discussionmentioning

confidence: 99%

Time-predictable chip-multiprocessor design

Schoeberl

2010

2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers

Self Cite

View full text Add to dashboard Cite

Abstract-Real-time systems need time-predictable platforms to enable static worst-case execution time (WCET) analysis. Improving the processor performance with superscalar techniques makes static WCET analysis practically impossible. However, most real-time systems are multi-threaded applications and performance can be improved by using several processor cores on a single chip. In this paper we present a time-predictable chipmultiprocessor system that aims to improve system performance while still enabling WCET analysis.The proposed chip-multiprocessor (CMP) uses a shared memory with a time-division multiple access (TDMA) based memory access scheduling. The static TDMA schedule can be integrated into the WCET analysis. Experiments with a JOP based CMP showed that the memory access starts to dominate the execution time when using more than 4 processor cores. To provide a better scalability, more local memories have to be used. We add a processor local scratchpad memory and split data caches, which are still time-predictable, to the processor cores.

show abstract

“…The embedded benchmarks Kfl and Lift are based on real-world applications [32]. The benchmark UdpIp uses a TCP/IP stack, implemented in Java, in order to simulate a UDP-based client/server application.…”

Section: Evaluation Methodologymentioning

confidence: 99%

Design Space Exploration for Java Processors with Cross-Profiling

Schoeberl

Binder

Moret

et al. 2009

2009 Sixth International Conference on the Quantitative Evaluation of Systems

Self Cite

View full text Add to dashboard Cite

Abstract-Most processors are used in embedded systems, where the processor architectures are diverse due to optimizations for different application domains. The main challenge for embedded system processors is the right balance between performance and chip size, which directly relates to cost. An early estimation of the performance for a new design is of paramount importance. In this paper we propose crossprofiling for that performance estimation, which can be accomplished very early in the design phase. We evaluate our approach in the context of a Java processor for embedded systems using cross-profiling on a standard desktop Java virtual machine. We explore the performance impact of various processor design choices and optimizations, such as different caches strategies or pipeline organizations, and come up with an improved processor design that yields speedups of up to 40% on standard Java benchmarks. Comparing the generated crossprofiles with the execution of benchmarks in real hardware confirms that our approach is sound.

show abstract

Application Experiences with a Real-Time Java Processor

Cited by 20 publications

References 14 publications

Data cache organization for accurate timing analysis

Data cache organization for accurate timing analysis

Time-predictable chip-multiprocessor design

Design Space Exploration for Java Processors with Cross-Profiling

Contact Info

Product

Resources

About